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zilog worldwide headquarters ? 910 e. hamilton avenue ? campbell, ca 95008 telephone: 408.558.8500 ? fax: 408.558.8300 ? www .zilog.com product speci?cation the muze family of z8 microcontrollers m aximum m emory with uart and z i log e xpandable eprom preliminary ps004005-1100
preliminary ps004005-1100 ?2000 by zilog, inc. all rights reserved. information in this publication concerning the devices, applica- tions, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. except with the express written approval of zilog, use of information, devices, or technology as critical components of life support systems is not authorized. no licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary iii table of contents architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 muze features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 expanded register file, bank 0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 asci registersexpanded register file, bank ah . . . . . . . . . . . . . . . . . . 61 expanded register file, bank fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 one-time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . . . . . . . . . 105 asci key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 asci interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 in-circuit serial programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 in-circuit serial programming block diagram . . . . . . . . . . . . . . . . . . . . . . 125 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 part number description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 precharacterization product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 document information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 document number description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 change log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 customer feedback form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 muze product specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 customer information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 product information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 return information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 problem description or suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary iv list of figures figure 1. muze functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. 20-pin dip/soic pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. 20-pin dip/soic pin configurationicsp mode . . . . . . . . . . . . . . . 6 figure 4. 28-pin dip/soic pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. 28-pin dip/soic pin configurationicsp mode . . . . . . . . . . . . . . . 9 figure 6. 40-pin dip/soic pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. 40-pin dip/soic pin configurationicsp mode . . . . . . . . . . . . . . 13 figure 8. 44-pin pqfp pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9. 44-pin pqfp pin configurationicsp mode . . . . . . . . . . . . . . . . . 17 figure 10. port 0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. port 1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. port 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 13. port 3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 14. port 3 configurationpcon register detail . . . . . . . . . . . . . . . . . 27 figure 15. program memory map for the muze family . . . . . . . . . . . . . . . . . . 30 figure 16. data memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 17. register pointerdetail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 18. expanded register file architecture . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 19. counter/timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 20. oscillator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 21. stop-mode recovery source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 22. resets and watch-dog timer example . . . . . . . . . . . . . . . . . . . . . 48 figure 23. typical low-voltage protection vs. temperature . . . . . . . . . . . . . . 49 figure 24. interrupt block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 25. external i/o or memory read and write timing . . . . . . . . . . . . . . . 86 figure 26. additional timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 27. input handshake timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 28. output handshake timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 29. test load diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 30. receive data register fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 31. fifo overrun example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 32. clear fifo overrun example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 33. asci interface diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 34. asci serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary v figure 35. multiprocessor mode serial data format . . . . . . . . . . . . . . . . . . . 115 figure 36. icsp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 37. icsp connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 38. 20-pin dip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 39. 20-pin soic package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 40. 28-pin dip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 41. 28-pin soic package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 42. 40-pin dip package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 43. 44-pin pqfp package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 132
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary vi list of tables table 1. muze family features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table 2. 20-pin dip/soic pin identification . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. 20-pin dip/soic pin identificationicsp mode . . . . . . . . . . . . . . . 6 table 4. 28-pin dip/soic pin identification . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. 28-pin dip/soic pin identificationicsp mode . . . . . . . . . . . . . . . 9 table 6. 40-pin dip/soic pin identification . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. 40-pin dip/soic pin identificationicsp mode . . . . . . . . . . . . . . 13 table 8. 44-pin pqfp pin identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. 44-pin pqfp pin identificationicsp mode . . . . . . . . . . . . . . . . . 17 table 10. port 3 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. register pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12. interrupt types, sources, and vectors . . . . . . . . . . . . . . . . . . . . . . 36 table 13. irq register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 14. port configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 15. stop-mode recovery register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 16. stop-mode recovery source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 17. stop-mode recovery register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 18. stop-mode recovery register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 19. watch-dog timer mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 20. wdt time select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 21. maximum (v lv ) conditions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 22. expanded register file registersreset states . . . . . . . . . . . . . . 50 table 23. timer mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 24. counter/timer 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 25. prescaler 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 26. counter/timer 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 27. prescaler 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 28. port 2 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 29. port 3 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 30. ports 0 and 1 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 31. interrupt priority register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 32. interrupt request register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 33. interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 34. flags register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary vii table 35. register pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 36. stack pointer high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 37. stack pointer low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 38. expanded register file registersreset states 61 table 39. transmit data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 40. receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 41. control register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 42. control register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 43. extension control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 44. time constant low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 45. time constant register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 46. status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 47. expanded register file registersreset states 68 table 48. port configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 49. verify register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 50. stop-mode recovery register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 51. stop-mode recovery register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 52. watch-dog timer mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 53. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 54. dc electrical characteristics at standard temperature . . . . . . . . . 76 table 55. dc electrical characteristics at extended temperature . . . . . . . . . 81 table 56. memory read and write timingstandard temperature . . . . . . . 87 table 57. memory read and write timingextended temperature . . . . . . . 89 table 58. additional timing at standard temperature . . . . . . . . . . . . . . . . . . 92 table 59. additional timing at extended temperature . . . . . . . . . . . . . . . . . . 95 table 60. handshake timing1 at standard temperature . . . . . . . . . . . . . . . . 98 table 61. handshake timing1 at extended temperature . . . . . . . . . . . . . . . . 99 table 62. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 63. option bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 64. asci interrupt conditions and sources . . . . . . . . . . . . . . . . . . . . . 110 table 65. transmit data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 66. receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 67. control register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 68. asci data format mode control bits . . . . . . . . . . . . . . . . . . . . . . 113 table 69. control register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 70. clock source and speed bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary viii table 71. extension control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 72. time constant register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 73. time constant register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 74. status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 75. baud rate list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 76. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary architectural overview 1 architectural overview zilogs large z8 ? family of 8-bit microcontrollers now includes the muze product line, featuring 4 kb to 64 kb of in-circuit serially-programmable (icsp) otp memory, an industry-standard universal asynchronous receiver/transmitter (uart), enhanced wake-up circuitry, programmable watch-dog timers (wdt), and low-noise/emi options. each of the new enhancements to the z8 offers a more ef?cient, cost-effective design and provides the user with increased design ?exibility over the standard z8 microcontroller core. the low-power-consumption otp microcontroller offers fast execution, ef?cient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion. the muze family features an expanded register file (erf) to allow access to register-mapped peripheral and i/o circuits. four basic address spaces are avail- able to support this wide range of con?gurations: program memory, register file, data memory, and erf. the register file is composed of 236 bytes contained within one general-purpose register (gpr), 4 i/o port registers, 15 control regis- ters, and status registers. the erf consists of 12 control registers. for applications demanding powerful i/o capabilities, the z86e122/e123/e124/ e125/e126 offers 16 pins, the z86e132/e133/e134/e135/e136 offers 24 pins, and the z86e142/e143/144/e145/e146 offers 32 pins dedicated to input and out- put. these lines are con?gurable under software control to provide timing, status signals, parallel i/o with or without handshake, and address/data bus for interfac- ing external memory. the muze family operates at 16mhz with a voltage range of 4.5 to 5.5v dc and up to 12mhz with a voltage range of 3.0 to 5.5v dc . to unburden the system from coping with real-time tasks such as counting/timing and data communication, the z8 offers two on-chip counter/timers with a large number of user-selectable modes and a hardware uart. with rom/romless selectivity, the z86e142/e143/e144/e145/e146 provides both external memory and icsp, which enables this z8 ? mcu to be used in high- volume applications, or where code ?exibility is required. all signals with an o v er line are active low. for example, b/w , for which word is active low, and b /w, for which byte is active low. power connections follow these conventional descriptions: connection circuit device power v cc v dd ground gnd v ss note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary architectural overview 2 muze features ? 4 kb to 64 kb otp memory ? full-duplex uart asynchronous serial communications interface (asci) ? dedicated 16-bit baud rate generator (brg) ? in-circuit serial programming interface ? 20-pin dip and 20-pin soic (e122, e123, e124, e125, e126) ? 28-pin dip and 28-pin soic (e132, e133, e134, e135, e136) ? 40-pin dip and 44-pin pqfp packages (e142, e143, e144, e145, e146) ? 3.0- to 5.5-volt operating range table 1. muze family features device otp (kb) ram* (bytes) speed 4.5v to 5.5v (mhzstandard and extended temperature) speed 3.0v to 5.5v (mhzstandard temperature only) z86e122 4 236 16 12 z86e123 8 236 16 12 z86e124 16 236 16 12 z86e125 32 236 16 12 z86e126 64 236 16 12 z86e132 4 236 16 12 z86e133 8 236 16 12 z86e134 16 236 16 12 z86e135 32 236 16 12 z86e136 64 236 16 12 z86e142 4 236 16 12 z86e143 8 236 16 12 z86e144 16 236 16 12 z86e145 32 236 16 12 z86e146 64 236 16 12 note: *general-purpose.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary architectural overview 3 ? operating temperature ranges: standard: 0oc to 70oc extended: C40oc to +105oc the extended temperature range is only for the 4.5- to 5.5-volt part, at 16- mhz max. operation. ? expanded register file (erf) ? 16 input/output lines (e122, e123, e124, e125, e126) 24 input/output lines (e132, e133, e134, e135, e136) 32 input/output lines (e142, e143, e144, e145, e146) ? vectored, prioritized interrupts with programmable polarity ? two analog comparators ? two programmable 8-bit counter/timers, each with a 6-bit programmable prescaler ? vbo/power-on reset (por) ? clock-free watch-dog timer (wdt) reset ? on-chip oscillator that accepts a crystal, ceramic resonator, lc, rc, or external clock ? ram and eprom protect ? optional 32-khz oscillator note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary architectural overview 4 functional block diagram figure 1. muze functional block diagram in-circuit serial prog port 3 counter/ timers (2) interrupt control two analog comparators port 2 i/o (bit programmable) alu flag register pointer register file machine timing & inst. control reset wdt, por program memory program counter v gnd 44 port 0 as ds r/w reset output input port 1 8 address or i/o (nibble programmable) address/data or i/o (byte programmable) (e142/e143/e144/e145/e416 only) (e142/e143/e144/ e145/e146 only) cc full-duplex uart 16-bit baud rate generator x in x out
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin description 5 pin description figure 2. 20-pin dip/soic pin con?guration table 2. 20-pin dip/soic pin identi?cation pin # symbol function direction 1C4 p24Cp27 port 2, bits 4,5,6,7 input/output 5v cc power supply 6x out crystal oscillator output 7x in crystal oscillator input 8C10 p31Cp33 port 3, bits 1,2,3 fixed input 11 p37 port 3, bit 7 fixed output 12 p30 port 3, bit 0 fixed input 13C15 p00Cp02 port 0, bits 0,1,2 input/output 16 gnd ground 17C20 p20Cp23 port 2, bits 0,1,2,3 input/output p24 p25 p26 p27 v cc x out x in p31 p32 p33 p23 p22 p21 p20 gnd p02 p01 p00 p30 p37 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 z86e122 z86e123 z86e124 z86e125 z86e126
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin description 6 figure 3. 20-pin dip/soic pin con?gurationicsp mode table 3. 20-pin dip/soic pin identi?cationicsp mode pin # symbol function direction 1C4 nc no connection 5v cc power supply 6C12 nc no connection 13 sck serial icsp clock input 14 sdio serial data input/output 15 icsp_reset icsp reset input 16 gnd ground 17C20 nc no connection nc nc nc nc v cc nc nc nc nc nc nc nc nc nc gnd icsp_reset sdio sck nc nc 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 z86e122 z86e123 z86e124 z86e125 z86e126
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin description 7 figure 4. 28-pin dip/soic pin con?guration table 4. 28-pin dip/soic pin identi?cation pin # symbol function direction 1C3 p25 port 2, bit 5 input/output 2 p26 port 2, bit 6 input/output 3 p27 port 2, bit 7 input/output 4 p04 port 0, bit 4 input/output 5 p05 port 0, bit 5 input/output 6 p06 port 0, bit 6 input/output 7 p07 port 0, bit 7 input/output 8v cc power supply 9x out crystal oscillator output 10 x in crystal oscillator input 11 p31 port 3, bit 1 fixed input 12 p32 port 3, bit 2 fixed input 13 p33 port 3, bit 3 fixed input 14 p34 port 3, bit 4 fixed output 15 p35 port 3, bit 5 fixed output 16 p37 port 3, bit 7 fixed output p25 p26 p27 p04 p05 p06 p07 v cc x out x in p31 p32 p33 p34 p24 p23 p22 p21 p20 p03 gnd p02 p01 p00 p30 p36 p37 p35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 z86e132 z86e133 z86e134 z86e135 z86e136
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin description 8 17 p36 port 3, bit 6 fixed output 18 p30 port 3, bit 0 fixed input 19 p00 port 0, bit 0 input/output 20 p01 port 0, bit 0 input/output 21 p02 port 0, bit 2 input/output 22 gnd ground 23 p03 port 0, bit 3 input/output 24 p20 port 2, bit 0 input/output 25 p21 port 2, bit 1 input/output 26 p22 port 2, bit 2 input/output 27 p33 port 2, bit 3 input/output 28 p24 port 2, bit 4 input/output table 4. 28-pin dip/soic pin identi?cation (continued) pin # symbol function direction
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin description 9 figure 5. 28-pin dip/soic pin con?gurationicsp mode table 5. 28-pin dip/soic pin identi?cationicsp mode pin # symbol function direction 1 nc no connection 2 nc no connection 3 nc no connection 4 nc no connection 5 nc no connection 6 nc no connection 7 nc no connection 8v cc power supply 9 nc no connection 10 nc no connection 11 nc no connection 12 nc no connection 13 nc no connection 14 nc no connection 15 nc no connection 16 nc no connection 17 nc no connection nc nc nc nc nc nc nc v cc nc nc nc nc nc nc nc nc nc nc nc nc gnd icsp_reset sdio sck nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 z86e132 z86e133 z86e134 z86e135 z86e136
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin description 10 18 nc no connection 19 sck serial icsp clock input 20 sdio serial data input/output 21 icsp_reset icsp reset input 22 gnd ground 23 nc no connection 24 nc no connection 25 nc no connection 26 nc no connection 27 nc no connection 28 nc no connection table 5. 28-pin dip/soic pin identi?cationicsp mode (continued) pin # symbol function direction
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin description 11 figure 6. 40-pin dip/soic pin con?guration table 6. 40-pin dip/soic pin identi?cation pin # symbol function direction 1r/w read/write output 2 p25 port 2, bit 5 input/output 3 p26 port 2, bit 6 input/output 4 p27 port 2, bit 7 input/output 5 p04 port 0, bit 4 input/output 6 p05 port 0, bit 5 input/output 7 p06 port 0, bit 6 input/output 8 p14 port 1, bit 4 input/output 9 p15 port 1, bit 5 input/output 10 p07 port 0, bit 7 input/output 11 v cc power supply 12 p16 port 1, bit 6 input/output 13 p17 port 1, bit 7 input/output r/w p25 p26 p27 p04 p05 p06 p14 p15 p07 v cc p16 p17 x out x in p31 p32 p33 p34 as ds p24 p23 p22 p21 p20 p03 p13 p12 gnd p02 p11 p10 p01 p00 p30 p36 p37 p35 reset z86e142 z86e143 z86e144 z86e145 z86e146 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin description 12 14 x out crystal oscillator output 15 x in crystal oscillator input 16 p31 port 3, bit 1 input 17 p32 port 3, bit 2 input 18 p33 port 3, bit 3 input 19 p34 port 3, bit 4 output 20 as address strobe output 21 reset reset input 22 p35 port 3, bit 5 output 23 p37 port 3, bit 7 output 24 p36 port 3, bit 6 output 25 p30 port 3, bit 0 input 26 p00 port 0, bit 0 input/output 27 p01 port 0, bit 1 input/output 28 p10 port 1, bit 0 input/output 29 p11 port 1, bit 1 input/output 30 p02 port 0, bit 2 input/output 31 gnd ground 32 p12 port 1, bit 2 input/output 33 p13 port 1, bit 3 input/output 34 p03 port 0, bit 3 input/output 35 p20 port 2, bit 0 input/output 36 p21 port 2, bit 1 input/output 37 p22 port 2, bit 2 input/output 38 p23 port 2, bit 3 input/output 39 p24 port 2, bit 4 input/output 40 ds data strobe output table 6. 40-pin dip/soic pin identi?cation (continued) pin # symbol function direction
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin description 13 figure 7. 40-pin dip/soic pin con?gurationicsp mode table 7. 40-pin dip/soic pin identi?cationicsp mode pin # symbol function direction 1 nc no connection 2 nc no connection 3 nc no connection 4 nc no connection 5 nc no connection 6 nc no connection 7 nc no connection 8 nc no connection 9 nc no connection 10 nc no connection 11 v cc power supply 12 nc no connection 13 nc no connection nc nc nc nc nc nc nc nc nc nc v cc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc gnd icsp_reset nc nc sdio sck nc nc nc nc reset z86e142 z86e143 z86e144 z86e145 z86e146 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin description 14 14 nc no connection 15 nc no connection 16 nc no connection 17 nc no connection 18 nc no connection 19 nc no connection 20 nc no connection 21 reset reset input 22 nc no connection 23 nc no connection 24 nc no connection 25 nc no connection 26 sck serial icsp clock input 27 sdio serial data input/output 28 nc no connection 29 nc no connection 30 icsp_reset icsp reset input 31 gnd ground 32 nc no connection 33 nc no connection 34 nc no connection 35 nc no connection 36 nc no connection 37 nc no connection 38 nc no connection 39 nc no connection 40 nc no connection table 7. 40-pin dip/soic pin identi?cationicsp mode (continued) pin # symbol function direction
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin description 15 figure 8. 44-pin pqfp pin con?guration table 8. 44-pin pqfp pin identi?cation pin # symbol function direction 1 p05 port 0, bit 5 input/output 2 p06 port 0, bit 5 input/output 3 p14 port 1, bit 4 input/output 4 p15 port 1, bit 5 input/output 5 p07 port 0, bit 7 input/output 6v cc power supply 7v cc power supply 8 p16 port 1 bit 6 input/output 9 p17 port 1 bit 7 input/output 10 x out crystal oscillator output 11 x in crystal oscillator input 12 p31 port 3, bit 1 input 13 p32 port 3, bit 2 input 14 p33 port 3, bit 3 input 34 35 36 37 38 39 40 41 42 43 44 p21 p22 p23 p24 ds nc r/w p25 p26 p27 p04 p30 p36 p37 p35 reset r/rl as p34 p33 p32 p31 p05 p06 p14 p15 p07 v cc v cc p16 p17 x out x in p20 p03 p13 p12 gnd gnd p02 p11 p10 p01 p00 1 23 33 z86e142 z86e143 z86e144 z86e145 z86e146 11 22 21 20 19 18 17 16 15 14 13 12 32 31 30 29 28 27 26 25 24 2345678910
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin description 16 15 p34 port 3, bit 4 output 16 as address strobe output 17 r/rl rom/romless control input 18 reset reset input 19 p35 port 3, bit 5 output 20 p37 port 3, bit 7 output 21 p36 port 3, bit 6 output 22 p30 port 3, bit 0 input 23 p00 port 0, bit 0 input/output 24 p01 port 0, bit 0 input/output 25 p10 port 1, bit 0 input/output 26 p11 port 1, bit 1 input/output 27 p02 port 0, bit 2 input/output 28 gnd ground 29 gnd ground 30 p12 port 1, bit 2 input/output 31 p13 port 1, bit 3 input/output 32 p03 port 0, bit 3 input/output 33 p20 port 2, bit 0 input/output 34 p21 port 2, bit 1 input/output 35 p22 port 2, bit 2 input/output 36 p23 port 2, bit 3 input/output 37 p24 port 2, bit 4 input/output 38 ds data strobe output 39 nc not connected 40 r/w read/write output 41 p25 port 2, bit 5 input/output 42 p26 port 2, bit 6 input/output 43 p27 port 2, bit 7 input/output 44 p04 port 0, bit 4 input/output table 8. 44-pin pqfp pin identi?cation (continued) pin # symbol function direction
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin description 17 figure 9. 44-pin pqfp pin con?gurationicsp mode table 9. 44-pin pqfp pin identi?cationicsp mode pin # symbol function direction 1 nc no connection 2 nc no connection 3 nc no connection 4 nc no connection 5 nc no connection 6v cc power supply 7v cc power supply 8 nc no connection 9 nc no connection 10 nc no connection 11 nc no connection 12 nc no connection 13 nc no connection nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc reset nc nc nc nc nc nc nc nc nc nc nc v cc v cc nc nc nc nc nc nc nc nc gnd gnd icsp_reset nc nc sdata sck 34 35 36 37 38 39 40 41 42 43 44 1 23 33 z86e142 z86e143 z86e144 z86e145 z86e146 11 22 21 20 19 18 17 16 15 14 13 12 32 31 30 29 28 27 26 25 24 2345678910
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin description 18 14 nc no connection 15 nc no connection 16 nc no connection 17 nc no connection 18 reset reset input 19 nc no connection 20 nc no connection 21 nc no connection 22 nc no connection 23 sck serial clock input 24 sdio serial data input/output 25 nc no connection 26 nc no connection 27 icsp_reset programming mode input 28 gnd ground 29 gnd ground 30 nc no connection 31 nc no connection 32 nc no connection 33 nc no connection 34 nc no connection 35 nc no connection 36 nc no connection 37 nc no connection 38 nc no connection 39 nc no connection 40 nc no connection 41 nc no connection table 9. 44-pin pqfp pin identi?cationicsp mode (continued) pin # symbol function direction
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin description 19 42 nc no connection 43 nc no connection 44 nc no connection table 9. 44-pin pqfp pin identi?cationicsp mode (continued) pin # symbol function direction
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin functions 20 pin functions the following pages describe the function of each available muze family pin. r/rl (input). the rom/romless pin, when connected to gnd, disables the inter- nal rom and forces the device to function as a romless z8. (available for devices in the 44-pin pqfp package only.) when left unconnected or pulled high to v cc , the device functions normally as a z8 rom version. when using the device in rom mode in a high-emi (noisy) environment, the romless pins must be connected directly to v cc . ds (output, active low). the data strobe is activated one time for each external memory transfer. for a read operation, data must be available prior to the trail- ing edge of ds . for write operations, the falling edge of ds indicates that out- put data is valid. (not available for devices in the 28-pin package.) as (output, active low). the address strobe is pulsed one time at the beginning of each machine cycle for external memory transfer. address output is from port 0/port 1 for all external programs. memory address transfers are valid at the trail- ing edge of as . under program control, as is placed in the high-impedance state along with ports 0 and 1, data strobe, and read/write. (not available for devices in the 28-pin package.) x in crystal input. this pin connects a parallel-resonant crystal, ceramic resonator, lc, or rc network, or an external single-phase clock to the on-chip oscillator input. x out crystal output. this pin connects a parallel-resonant crystal, ceramic reso- nant, lc, or rc network to the on-chip oscillator output. r/w (output, write low). the read/write signal is high when the z8 reads from external program or data memory. the signal is low when the z8 writes to external data memory. (not available for devices in the 28-pin package.) port 0 (p00Cp07). port 0 is an 8-bit, bidirectional, cmos-compatible port. these eight i/o lines are con?gured under software control as a nibble i/o port (p03C p00 input/output and p07Cp04 input/output), or as an address port for interfacing external memory. the input buffers are schmitt-triggered and nibble-programmed as outputs and can be globally programmed as either push-pull or open-drain. low-emi output buffers are globally programmed by the software. port 0 may be placed under handshake control. in this con?guration, port 3, lines p32 and p35 are used as the handshake control d a v0 and rdy0. handshake signal direction is dictated by the i/o direction (input or output) of port 0 of the upper nibble p04C p07. the lower nibble must indicate the same direction as the upper nibble. for external memory references, port 0 provides address bits a11Ca8 (lower nib- ble) and a15Ca8 (lower and upper nibble) depending on the required address notes:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin functions 21 space. if the address range requires 12 bits or less, the upper nibble of port 0 is programmed independently as i/o while the lower nibble is used for addressing. if one or both nibbles are required for i/o operation, they are con?gured by writing to the port 0 mode register. in romless mode, after a hardware reset, port 0 is con?gured as address lines a15Ca8, and extended timing is set to accommodate slow memory access. the initialization routine can include recon?guration to eliminate this extended timing mode. (in rom mode, port 0 is de?ned as input after reset.) port 0 can be placed in a high-impedance state along with port 1, as , ds and r/ w , allowing the z8 to share common resources in multiprocessor and dma appli- cations (figure 10). figure 10. port 0 con?guration port 0 (i/o or a15?8) handshake controls dav0 and rdy0 (p32 and p35) z8 4 4 open-drain oe out in 1.5 2.3 hysteresis @ v = 5.0v pad pull-up transistor enable (programmable option) auto latch (mask option) r 500k ? cc
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin functions 22 port 1 (p17Cp10). port 1 is an 8-bit, bidirectional, cmos- compatible port (figure 11), with multiplexed address (a7Ca0) and data (d7Cd0) ports. these 8 i/ o lines are programmed as inputs or outputs, or can be con?gured under software control as an address/data port for interfacing external memory. the input buffers are schmitt-triggered and byte-programmed as outputs and can be globally pro- grammed as either push-pull or open-drain. low-emi output buffers are globally programmed by the software. port 1 is not available on the devices in the 28-pin package, and p01m register must set bit d4,d3 as 00. low-emi mode is not supported on the emulator for port1. pcon register d4 must be 1. port 1 may be placed under handshake control. in this con?guration, port 3, lines p33 and p34 are used as the handshake controls rdy1 and d a v1 (ready and data available). memory locations greater than the internal rom address are referenced through port 1, except for the z86e146 (due to its 64 kb of internal memory). to interface external memory, port 1 must be programmed for multiplexed address/data mode. if more than 256 external locations are required, port 0 outputs the addi- tional lines. port 1 can be placed in the high-impedance state along with port 0, as , ds , and r/w , allowing the z8 to share common resources in multiprocessor and dma applications. note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin functions 23 port 2 (p27Cp20). port 2 is an 8-bit, bidirectional, cmos-compatible i/o port. these eight i/o lines are con?gured under software control as an input or output, independently. port 2 is always available for i/o operation. the input buffers are schmitt-triggered. bits programmed as outputs may be globally programmed as either push-pull or open-drain. low-emi output buffers are globally programmed by the software. port 2 may be placed under handshake control. in handshake mode, port 3 lines p31 and p36 are used as the handshake control lines d a v2 and rdy2. the handshake signal assignment for port 3 lines p31 and p36 is dictated by the direction (input or output) assigned to bit 7, port 2 (figure 12). figure 11. port 1 con?guration open drain oe out in 1.5 2.3 hysteresis @ v cc = 5.0v pa d auto latch (mask option) r 500 k ? port 1 (i/o or ad7 ad0) handshake controls dav1 and rdy1 (p33 and p34) z8 8 pull-up transistor enable (programmable option)
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin functions 24 port 3 (p37Cp30). port 3 is an 8-bit, cmos-compatible port, with four ?xed inputs (p33Cp30) and four ?xed outputs (p34Cp37). port 3 is con?gured under software control for input/output, counter/timers, interrupt, uart, port handshake, and data memory functions. port 3, bit 0 input is schmitt-triggered, and pins p31, p32, and p33 are standard cmos inputs (no autolatches). pins p34, p35, p36, p37 are push-pull output lines. low-emi output buffers are globally programmed by the software. two onboard comparators process analog signals on p31 and p32 with reference to the voltage on p33. the analog function is enabled by programming port 3 mode register (p3m bit 1). for interrupt functions, port 3, bit 0 and pin 3 are fall- ing-edge interrupt inputs. p31 and p32 are programmable as rising, falling, or both edge-triggered interrupts (irq register bits 6 and 7). p33 is the comparator reference voltage input when in analog mode. access to counter/timer 1 is made figure 12. port 2 con?guration open drain oe out in 1.5 2.3 hysteresis @ v cc = 5.0v pad auto latch (mask option) port 2 (i/o) handshake controls z8 r 500 k ? dav2 and rdy2 (p31 and p36) pull-up transistor enable (programmable option)
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin functions 25 through p31 (t in ) and p36 (t out ). handshake lines for ports 0, 1, and 2 are avail- able on p31 through p36. port 3 also provides the following control functions: handshake for ports 0, 1, and 2 (d a v and rdy); four external interrupt request signals (irq3Cirq0); timer input and output signals (t in and t out ); data memory select (dm , see table 10 and figure 13). p34 output is software-programmed to function as a data memory select (dm ). the port 3 mode register (p3m) bit d3,d4 selects this function. when accessing external data memory, p34 goes active low; when accessing external program memory, p34 goes high. an onboard uart (asci) is enabled by software by setting the re and te bits of the asci control register a (cntla). when enabled, p30 is the receive input and p37 is the transmit output. comparator inputs and outputs. port 3, pins p31 and p32 each feature a compar- ator front end. the comparator reference voltage, pin p33, is common to both comparators. in analog mode, the p31 and p32 are the positive inputs to the comparators, and p33 is the reference voltage supplied to both comparators. in digital mode, pin p33 is used as a p33 register input or irq1 source. p34 and p37 can provide the comparator output directly by software-programming the pcon register bit d0 to 1 (see figure 14). table 10. port 3 pin assignments pin i/o control timer analog interrupt p0 hs p1 hs p2 hs ext uart p30 in irq3 rx p31 in t in an1 irq2 d/r p32 in an2 irq0 d/r p33 in ref irq1 d/r p34 out an1Cout r/d dm p35 out r/d p36 out t out r/d p37 out an2Cout tx notes: hs = handshake signals d = da v r = rdy
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin functions 26 the user must add a two-nop delay after setting the p3m bit d1 to 1 before the comparator output is valid. irq0, irq1, and irq2 must be cleared in the irq register when the comparator is enabled or disabled. figure 13. port 3 con?guration note: d1 r247 = p3m p31 (an1) p32 (an2) p33 (ref) from stop-mode recovery source 1 = analog 0 = digital irq2, t , p31 data latch in irq0, p32 data latch irq1, p33 data latch dig. an. auto latch (progammable option) p30 data latch irq3 port 3 (i/o or control) z8 + + p30 r 500k ? p30 p31 p32 p33 p34 p35 p37 p36
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin functions 27 autolatch. the autolatch places valid cmos levels on all cmos inputs (except p33Cp31) that are not externally driven. whether this level is 0 or 1 cannot be determined. a valid cmos level, rather than a ?oating node, reduces excessive supply current ?ow in the input buffer. autolatches are available on port 0, port 1, port 2, and p30. there are no autolatches on p31, p32, and p33. deletion of all port autolatches is available as an option when the device is programmed. the autolatch disable option is selected by the customer when the device is programmed. reset (input/output, active low). initializes the mcu. reset occurs through power-on reset, watch-dog timer reset, stop-mode recovery, or external reset. during power-on reset and watch-dog reset, the internally-generated reset drives the reset pin low for the por time. pull-up is provided internally. any devices driving the reset line must be open-drain to avoid damage from a possible con?ict during reset conditions. reset depends on os- cillator operation to achieve full reset conditions, except for conditions wherein the reset is caused by a wdt time-out. the reset pin is not available on devices in the 28-pin package. figure 14. port 3 con?gurationpcon register detail p34 out p31 + C ref (p33) p34 pa d p37 out p32 + C ref (p33) 0 p34, p37 standard output 1 p34, p37 comparator output pcon d0 p37 pa d note: caution: note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary pin functions 28 after the por time, reset is a schmitt-triggered input. during the reset cycle, ds is held active low while as cycles at a rate of t p c 2. program execution begins at location 000ch , after the reset is released. for power-on reset, the reset output time is t por ms. when program execution begins, as and ds toggles only for external memory accesses. the z8 does not reset wdtmr, smr, p2m, pcon, and p3m registers on a stop-mode recovery operation or from a wdt reset out of stop mode.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 29 functional description the z8 mcu incorporates the following functions that enhance the standard z8 ? architecture and provide the user with increased design ?exibility: ? reset ? program memory ? data memory ? eprom protect ? ram protect ? working register file ? expanded register file ? general-purpose registers ? stack pointer ? counter/timers ? interrupts ? clock ? power-on reset ? halt and stop modes ? port con?guration register ? comparator ? stop-mode recovery ? watch-dog timer ? voltage comparator reset. the device is reset in one of the following conditions: ? power-on reset ? watch-dog timer ? stop-mode recovery source ? external reset ? low voltage recovery
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 30 automatic power-on reset circuitry is built into the z8, eliminating the require- ment for an external reset circuit to reset upon power-up. the internal pull-up resistor is on the reset pin, so a pull-up resistor is not required; however, in a high-emi (noisy) environment, it is recommended that a low-value pull-up resistor be used. the reset pin is not available on devices in the 28-pin package. program memory. the ?rst 12 bytes of program memory are reserved for the inter- rupt vectors. these locations contain six 16-bit vectors that correspond to the six available interrupts. for rom mode, address 12 to address ffffh (e136/e146)/ 7fffh (e135/e145)/ 3fff (e134/e144) consists of programmable eprom. the z86e142/e143/e144/e145 can access external program and data memory from addresses 4000h/8000h to ffffh . see figure 15. figure 15. program memory map for the muze family note: 12 11 10 9 8 7 6 5 4 3 2 1 0 on-chip rom location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 irq5 3fffh/7fffh external/internal rom and ram ffffh 3ffeh/7ffeh
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 31 data memory (dm ). the romless version addresses up to 64 kb of external data memory. external data memory may be included with, or separated from, the external program memory space. dm , an optional i/o function that is programmed to appear on pin p34, is used to distinguish between data and program memory space (figure 16). the state of the dm signal is controlled by the type of instruc- tion being executed. an ldc op code references program (dm inactive) memory, and an lde instruction references data (dm active low) memory. the user must con?gure port 3 mode register (p3m) bits d3 and d4 for this mode. this feature is not usable for devices in 28-pin package. when used in rom mode, the z86e146 cannot access any external data or program memory. the z86e14x series of z8 mcus can access external program and data memory from addresses 4000h / 8000h to ffffh . figure 16. data memory map note: ffffh 4000h/8000h 0 external data memory external data memory not addressable 3fffh/7fffh eprom mode ffffh 0 romless mode
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 32 eprom protect. eprom protect provides an additional security function. when the device is programmed with the eprom protect option bit selected, and it is executing out of external program memory, instructions ldc, ldci, lde, and ldei cannot read internal program memory. when the eprom protect option bit is selected, and executing out of internal program memory, instructions ldc, ldci, lde, and ldei can read internal pro- gram memory. ram protect. the upper portion of the rams address spaces 80h to efh (exclud- ing the control registers) can be protected from writing. the ram protect option bit can be selected when the device is programmed. after the mask option is selected, the user activates this feature from the internal rom code to turn off/on the ram protect by loading either a 0 or a 1 into the imr register, bit d6. a 1 in bit d6 enables the ram protect option. working register file. the z8 standard register ?le contains 4 i/o port registers, 236 general-purpose registers, and 15 control and status registers. expanded register ?le fh contains 3 system-con?guration registers. expanded register ?le ah contains 8 asci control registers. the working registers are accessed directly or indirectly via an 8-bit address ?eld. as a result, a short 4-bit register address can use the register pointer (table 11 and figure 17). in the 4-bit mode, the working register ?le is divided into 16 working register groups, each occupying 16 continuous locations. the register pointer addresses the starting location of the active working register group. throughout this document, the z8 standard register file is referred to as a bank. expanded register file (erf). the z8 register ?le is expanded to allow for addi- tional system control registers, and for mapping of additional peripheral devices, along with the i/o ports, into the register address area. the z8 register address space r0 through r15 is implemented as 16 groups of 16 registers per bank (fig- table 11. register pointer registerrp fdh/r253 bank 0h: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0000 0 000 note: r = read, w = write, x = indeterminate. bit position bit field r/w state description d7Cd4 working registers r/w 0 working register group pointer d3Cd0 erf r/w 0 expanded register file
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 33 ures 17 and 18 ). these register groups are known as the expanded register file (erf). bits 7C4 of register rp select the working register group. bits 3C0 of reg- ister rp select the expanded register file. five system con?guration registers reside in the expanded register file at bank fh pcon, vfy, smr, smr2, and wdtmr. the 8 control registers for the asci are located in the expanded regis- ter file bank ah . the remainder of the expanded register is not physically imple- mented, and is open for future expansion. figure 17. register pointerdetail the upper nibble of the register file address provided by the register pointer specifies the active working-register group. r7 r6 r5 r4 r253 (register pointer) i/o ports specified working register file the lower nibble of the register file address provided by the instruction points to the specified register . r3 r2 r1 r0 register file1 register file 0 r15 to r0 r15 to r4* r3 to r0* ff f0 7f 70 6f 60 5f 50 4f 40 3f 2f 30 20 1f 10 0f 00 * expanded register file 0 is selected in this figure by handling bits d3 to d0 as "0" in register r253 (rp). ef 80 register bank fh
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 34 general-purpose registers (gpr). general-purpose registers are unde?ned after the device is powered up. these registers keep the most recent value after any reset, as long as the reset occurs in the v cc voltage-speci?ed operating range. general-purpose registers are not guaranteed to keep their most recent state from a low-voltage protection (v lv ) reset if v cc drops below 1.8v. register bank e0?f is only accessed via working register and indirect addressing modes. stack pointer. the z8 internal register ?le is used for the stack. the 16-bit stack pointer (sph and spl) is used for the external stack, which can reside anywhere in the data memory for romless mode. an 8-bit stack pointer (spl) is used for the internal stack that resides within the 236 general-purpose registers. stack pointer high (sph) is used as a general-purpose register only when using an internal stack. the devices in the 28-pin and 40-pin packages can only use the 8- bit stack pointer (spl) for the internal stack. sph and spl are set to 00h after any reset or stop-mode recovery. counter/timers. there are two 8-bit programmable counter/timers (t0Ct1), each driven by its own 6-bit programmable prescaler. the t1 prescaler is driven by internal or external clock sources; however, the t0 prescaler is driven by the inter- nal clock only (figure 19). the 6-bit prescalers can divide the input frequency of the clock source by any integer number from 2to 64. each prescaler drives its counter, which decrements the value (1 to 256) that is loaded into the counter. when the counter reaches the end of the count, a timer interrupt request, irq4 (t0) or irq5 (t1), is generated. the counters are programmed to start, stop, restart to continue, or restart from the initial value. the counters can also be programmed to stop upon reach- ing 0 (single-pass mode) or to automatically reload the initial value and con- tinue counting (moduloCn continuous mode). the counters, but not the prescalers , are read at any time without disturbing their value or count mode. the clock source for t1 is user-de?nable and is either the internal microprocessor clock divide-by-four, or an external signal input through port 3. the timer mode register con?gures the external timer input (p31) as an external clock, a trigger input that is retriggerable or nonretriggerable, or as a gate input for the internal clock. the counter/timers are cascaded by connecting the t0 output to the input of t1. t in mode is enabled by setting pre1 bit d1 to 0. note: note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 35 figure 18. expanded register file architecture 7 6543210 working register group pointer expanded register file pointer ffh foh 70h 0fh 00h z8 working register file register pointer ffh feh fdh fch fbh fah f9h f8h f7h* f6h* f5h f4h f3h f2h f1h f0h spl sph rp flags imr irq ipr p01m p3m p2m pre0 t0 pre1 t1 tmr 0 x 0 0 x 0 0 1 x x x x 0 0fh* 0eh 0dh* 0ch 0bh** 0ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h wdtmr smr 0 x x 0 x 1 0 1 x x x x 0 0 x x 0 x 0 0 1 x x x x 0 0 x x 0 x 0 0 1 x x x x 0 0 x x 0 x 1 0 1 x x x x 0 0 x x 0 x 1 0 1 x x x x 0 0 x x 0 x 0 0 1 x x 0 x 0 0 x x 0 x 1 0 1 0 x 0 x 0 xxx 01101 00100000 expanded register file fh working register group 0 reset condition expanded register file ah working register group 0 reset condition expanded register file 0h working register group 0 z8 standard control registers reset condition 0fh* reserved 0eh* reserved 0dh reserved 0ch reserved d7 d6 d5 d4 d3 d2 d1 d0 asci control registers reserved reserved smr2 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved pcon 11111110 notes: x = indeterminate. the romless reset condition: 10110110. *is not reset via stop-mode recovery. **is not reset via stop-mode recovery, excet for bit d0. not available on 28-pin packages. x 00000000 00000000 xxxxxx0 0 ? x ? 0bh* reserved 0ah* reserved 09h gpr 08h stat x 07h* asth 06h* astl 05h asext 04h cntlb x xxxxxxxx xxxxxxxx 00010000 00000111 x0000010 11111111 11111111 00000000 03h* cntla 02h* rdr 01h tdr 00h reserved x
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 36 interrupts. the z8 features six different interrupts from six different sources. these interrupts are maskable and prioritized ( figure 24 ). the 6 sources are divided as follows: 4 sources are claimed by port 3 lines p33Cp30, and 2 are claimed by counter/timers (table 12). the interrupt mask register globally or indi- vidually enables or disables the six interrupt requests. figure 19. counter/timer block diagram table 12. interrupt types, sources, and vectors name source vector location comments irq0 dav0 , irq0 0,1 external (p32), rising and falling edges triggered irq1, irq1 2,3 external (p33), falling edge triggered irq2 dav2 , irq2, t in 4,5 external (p31), rising and falling edges triggered pre0 initial value register t0 initial value register t0 current value register 6-bit down counter 8-bit down counter 16 4 6-bit down counter 8-bit down counter pre1 initial value register t1 initial value register t1 current value register 2 clock logic irq4 t p36 irq5 internal data bus write write read internal clock gated clock triggered clock tin p31 write write read internal data bus external clock internal clock d0 (smr) 4 2 osc d1 (smr) out
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 37 when more than one interrupt is pending, priorities are resolved by a programma- ble priority encoder that is controlled by the interrupt priority register. an interrupt machine cycle activates when an interrupt request is granted. this action disables all subsequent interrupts, saves the program counter and status flags, and then branches to the program memory vector location reserved for that interrupt. all z8 interrupts are vectored through locations in the program memory. this memory location and the next byte contain the 16-bit address of the interrupt ser- vice routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests require service. when in analog mode, an interrupt resulting from comparator1 maps to irq2, and an interrupt from comparator2 maps to irq0. interrupts irq2 and irq0 may be rising, falling, or both edge-triggered, and are programmed in the irq register. the software polls to identify the state of the pin. when in analog mode, irq1 is generated by the stop-mode recovery source selected by smr register bits d4, d3, d2, or smr2 d1 or d0. programming bits for the interrupt edge select are located in the irq register, bits d7 and d6. the con?guration is indicated in table 13. irq3 uart (asci) 6,7 external (p30), falling edge triggered irq4 t0 8,9 internal irq5 t1 10,11 internal table 13. irq register* irq interrupt edge d7 d6 p31 p32 00ff 01fr 10rf 11r/fr/f notes: f = falling edge r = rising edge table 12. interrupt types, sources, and vectors (continued) name source vector location comments
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 38 clock. the z8 on-chip oscillator features a high-gain, parallel-resonant ampli?er for connection to a crystal, lc, rc, ceramic resonator, or any suitable external clock source (x in = input, x out = output). the crystal should be at-cut, 16 mhz maximum, with a series resistance (rs) of less than or equal to 100 ? when oscillating from 1mhz to 16mhz. the crystal should be connected across x in and x out using the vendors recom- mended capacitor values from each pin directly to the device ground pin to reduce ground-noise injection into the oscillator. the rc oscillator option can be selected when the device is programmed. the rc option is available up to 8 mhz. the rc oscillator con?guration must be an external resistor connected from x in to x out , with a frequency- setting capacitor from x in to ground (figure 20). for better noise immunity, the capacitors should be tied directly to the device ground pin ( v ss ). power-on reset (por). a timer circuit clocked by a dedicated on-board rc oscilla- tor is used for the power-on reset (por) timer function. the por time allows v cc and the oscillator circuit to stabilize before instruction execution begins. the por timer circuit is a one-shot timer triggered by one of three conditions: 1. power fail to power ok status. 2. stop-mode recovery (if d5 of smr = 1). 3. wdt time-out. figure 20. oscillator con?guration note: x c1 c2 c1 c2 c1 ceramic resonator or crystal c1, c2 = 47 pf typ.* f = 8 mhz lc c1, c2 = 22 pf l = 130 h * f = 3 mhz * rc @ 5v v (typ.) c1 = 33 pf* r = 1 kb* f = 6 mhz* external clock lr *preliminary value, including pin parasitics. **device ground pin. v ** ss v ** ss v ** ss v ** ss v ** ss cc in x out x in x out x in x out x in x out
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 39 the por time is speci?ed as tpor. bit 5 of the stop-mode register determines whether the por timer is bypassed after stop-mode recovery (typical for exter- nal clock, rc/lc oscillators). halt. halt turns off the internal cpu clock, but not the crystal oscillation. the counter/timers, uart, and external interrupts irq0, irq1, irq2, and irq3 remain active. the devices are recovered by interrupts and are either externally or internally generated. an interrupt request must be enabled and executed to exit halt mode. after the interrupt service routine, the program continues from the instruction after the halt. in order to enter stop (or halt) mode, it is necessary to ?rst ?ush the instruc- tion pipeline to avoid suspending execution in mid-instruction. therefore, the user must execute a nop (op code = ffh ) immediately before the appropriate sleep instruction. for example: or stop. this instruction turns off the internal clock and external crystal oscillation. the stop instruction also reduces the standby current to 10 a or less. stop mode is terminated by a reset only, either by wdt time-out, por, stop-mode recovery, or external reset. as a result, the processor restarts the application pro- gram at address 000ch . a wdt time-out in stop mode affects all registers the same as if a stop-mode recovery occurred via a selected stop-mode recovery source except that the por delay is enabled even if the delay is selected for dis- able. if a permanent wdt is selected, the wdt runs in all modes and cannot be stopped or disabled if the onboard rc oscillator is selected to drive the wdt . port configuration register (pcon). the pcon register con?gures the ports indi- vidually; comparator output on port 3, open-drain on port 0 and port 1, low emi on ports 0, 1, 2, and 3, and low-emi oscillator. the pcon register is located in the expanded register ?le at bank f, location 00h (table 14). ff nop ; clear the pipeline 6f stop ; enter stop mode ff nop ; clear the pipeline 7f halt ; enter halt mode note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 40 comparator comparator output port 3 (d0). bit 0 controls the comparator use in port 3. a 1 in this location brings the comparator outputs to p34 and p37, and a 0 releases the port to its standard i/o con?guration. the default value is 0. port 1 open-drain (d1). port 1 is con?gured as an open-drain by resetting this bit (d1 = 0) or con?gured as push-pull active by setting this bit (d1 = 1). the default value is 1. the user must set d1 = 1 for devices in 28-pin packages. table 14. port con?guration registerpcon 00h/r0 bank fh: write only bit d7 d6 d5 d4 d3 d2 d1 d0 r/w wwww w www reset 1111 1 110 note: r = read, w = write, x = indeterminate. bit position bit field r/w state description d7 oscillator w 1 low-emi oscillator 0: low emi 1: standard d6 port 3 i/o w 1 port 3 0: low emi 1: standard d5 port 2 i/o w 1 port 2 0: low emi 1: standard d4 port 1 i/o w 1 port 1 0: low emi 1: standard d3 port 0 i/o w 1 port 0 * 0: low emi 1: standard d2 port 0 i/o w 1 port 0 0: open-drain 1: push-pull active d1 port 1 i/o w 1 port 1 * 0: open-drain 1: push-pull active d0 port 3 w 0 port 3 comparator output 0: p34, p37 standard output 1: p34, p37 comparator output note: must be set to 1 for devices in 28-pin packages.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 41 port 0 open-drain (d2). port 0 is con?gured as an open-drain by resetting this bit (d2 = 0) or con?gured as push-pull active by setting this bit (d2 = 1). the default value is 1. low-emi port 0 (d3). port 0 is con?gured as a low-emi port by resetting this bit (d3 = 0) or con?gured as a standard port by setting this bit (d3 = 1). the default value is 1. low-emi port 1 (d4). port 1 is con?gured as a low-emi port by resetting this bit (d4 = 0) or con?gured as a standard port by setting this bit (d4 = 1). the default value is 1. the user must set d4 = 1 for devices in 28-pin packages. for emulator, this bit must be set to 1. low-emi port 2 (d5). port 2 is con?gured as a low-emi port by resetting this bit (d5 = 0) or con?gured as a standard port by setting this bit (d5 = 1). the default value is 1. low-emi port 3 (d6). port 3 is con?gured as a low-emi port by resetting this bit (d6 = 0) or con?gured as a standard port by setting this bit (d6 = 1). the default value is 1. low-emi osc (d7). this bit of the pcon register controls the low-emi noise oscil- lator. a 1 in this location con?gures the oscillator, ds , as and r/w with standard drive, while a 0 con?gures the oscillator, ds , as and r/w with low noise drive. low-emi mode reduces the drive of the oscillator (osc). the default value is 1. maximum external clock frequency of 4 mhz when running in low-emi oscillator mode. low-emi emission. the z8 is programmed to operate in a low-emi emission mode in the pcon register. the oscillator and all i/o ports is programmed as low-emi emission mode independently. use of this feature results in: ? the pre-drivers slew rate reduced to 10 ns (typical) ? low-emi output drivers exhibit resistance of 200 ? (typical) ? low-emi oscillator ? internal sclk = crystal operation limited to a maximum of 4 mhzC250 ns cycle time, when low emi oscillator is selected and system clock (smr register bit d1 = 1) stop-mode recovery stop-mode recovery registers (smr1 and smr2). these registers select the clock divide value and determine the mode of stop-mode recovery (tables 15 and 18). all bits are write only, except bit 7 of smr1, which is read only. smr1 bit 7 is a ?ag bit that is set by hardware on a stop-mode recovery condition and note: note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 42 reset by a power-on cycle. for smr1, bit 6 controls whether a low level or a high level is required from the recovery source. bit 5 controls the reset delay after stop-mode recovery. bits 2, 3, and 4 of the smr1 register specify the source of the stop-mode recovery signal. bits 0 and 1 determine the time-out period of the wdt. the smr registers are located in bank f of the expanded register file at addresses 0bh and 0dh , respectively. for smr2, bits 7 to 2 are reserved. bits 1 and 0 of the smr2 register specify the source of the stop-mode recovery signal. table 15. stop-mode recovery register 1smr1 0bh/r11 bank fh : write only, except bit d7, which is read only bit d7 d6 d5 d4 d3 d2 d1 d0 r/w rwww w www reset 0010 0 000 note: r = read, w = write, x = indeterminate. bit position bit field r/w state description d7 stp r0 stop flag 0: por 1: stop-mode recovery d6 smr w0 stop-mode recovery level 0: low 1: high d5 stpdly w1 stop delay 0: off 1: on d0 clk w0 sclk tclk divide-by-16 0: off 1 1: on notes: 1. do not use in conjunction with smr2 source. 2. cleared by reset and smr.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 43 sclk tclk divide-by-16 select (d0). bit d0 of the smr controls a divide-by-16 prescaler of sclk tclk. the purpose of this control is to selectively reduce device power consumption during normal processor execution (sclk control) and/or halt mode (where tclk sources counter/timers and interrupt logic). this bit is reset to d0 = 0 after a stop-mode recovery. external clock divide-by-two (d1). this bit can eliminate the oscillator divide-by- two circuitry. when this bit is 0, the system clock (sclk) and timer clock (tclk) are equal to the external clock frequency divided by 2. the sclk is equal to the external clock frequency when this bit is set (d1 = 1). using this bit together with d7 of pcon further helps lower emi (that is, d7 (pcon) = 0, d1 (smr) = 1). the default setting is 0. maximum external clock frequency is 4 mhz when smr bit d1 = 1 where sclk tclk = crystal. stop-mode recovery source (d2, d3, and d4). these three bits of the smr specify the wake-up source of the stop-mode recovery (figure 21 and table 16). when the stop-mode recovery sources are selected in this register, then smr2 regis- ter bits d0,d1 must be set to 0. if the port 2 pin is con?gured as an output, this output level is read by the smr circuitry. d4Cd2 smrsrc w 000 stop-mode recovery source2 000: por only and/or external reset 001: p30 010: p31 011: p32 100: p33 101: p27 110: p2 nor 0C3 111: p2 nor 0C7 d1 extclk w0 external clock divide-by-2 0: sclk tclk = crystal 2 1: sclk = crystal d0 clk w0 sclk tclk divide-by-16 0: off 1 1: on notes: 1. do not use in conjunction with smr2 source. 2. cleared by reset and smr. note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 44 figure 21. stop-mode recovery source table 16. stop-mode recovery source smr[4C2] d4 d3 d2 operation/description of action 000 por and/or external reset recovery 001 p30 transition 010 p31 transition (not in analog mode) 011 p32 transition (not in analog mode) 100 p33 transition (not in analog mode) 101 p27 transition 110 logical nor of p20 through p23 111 logical nor of p20 through p27 p30 p31 p32 p33 p27 stop-mode recovery edge select (smr) p33 from pads digital/analog mode select (p3m) to p33 data latch and irq1 to por reset smr smr smr d4 d3 d2 0 0 1 0 1 0 0 1 1 d4 d3 d2 1 0 0 d4 d3 d2 1 0 1 mux smr smr d4 d3 d2 1 1 0 d4 d3 d2 1 1 1 p20 p23 p20 p27 smr2 smr2 d1 d0 0 1 d1 d0 1 0 p20 p23 p20 p27 smr d4 d3 d2 0 0 0 v smr2 d1 d0 0 0 dd v dd
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 45 stop-mode recovery delay select (d5). this bit, if high, enables the t por reset delay after stop-mode recovery. the default con?guration of this bit is 1. if the fast wake up is selected, the stop-mode recovery source must be kept active for at least 5 t p c. code execution begins after t edelay (see t ab les 58 and 59 ). stop-mode recovery edge select (d6). a 1 in this bit position indicates that a high level on any one of the recovery sources wakes the z8 from stop mode. a 0 indi- cates low-level recovery. the default is 0 on por (table 17). this bit is used for either smr or smr2. cold or warm start (d7). this bit is set by the device upon entering stop mode. a 0 in this bit (cold) indicates that the device resets by por/wdt reset. a 1 in this bit (warm) indicates that the device awakens by a stop-mode recovery source. if the port 2 pin is con?gured as an output, this output level is read by the smr2 circuitry. stop-mode recovery register 2 (smr2). this register contains additional stop- mode recovery sources. when the stop-mode recovery sources are selected in this register then smr register bits d2, d3, and d4 must be 0. table 17. stop-mode recovery register 2 smr1C0 d1 d0 operation/description of action 00 por and/or external reset recovery 01 logical and of p20 through p23 10 logical and of p20 through p27 table 18. stop-mode recovery register 2smr2 0dh/r13 bank fh: write only bit d7 d6 d5 d4 d3 d2 d1 d0 r/w wwww w www reset xxx x x x 0 0 note: r = read, w = write, x = indeterminate. bit/ field bit position r/w state description d7Cd2 reserved wx reservedmust be 0 d1Cd0 stop mode w00 stop-mode recovery source 2* 00: por only 01: and p20, p21, p22, p23 10: and p20, p21, p22, p23, p24, p25, p26, p27 note: *do not use in conjunction with smr source. note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 46 watch-dog timer watch-dog timer mode register (wdtmr). the wdt is a retriggerable one-shot timer that resets the z8 if it reaches its terminal count. the wdt is initially enabled by executing the wdt instruction and refreshed on subsequent execu- tions of the wdt instruction. the wdt circuit is driven by an onboard rc oscilla- tor or external oscillator from the x in pin. the por clock source is selected with bit 4 of the wdt register (table 19). wdt instruction affects the z (zero), s (sign), and v (over?ow) ?ags. the wdtmr must be written to within the ?rst 64 internal system clocks. after that, the wdtmr is write-protected. wdt time-out while in stop mode does not reset smr, pcon, wdtmr, p2m, p3m, ports 2 & 3 data registers, but the por delay counter is still enabled even though the smr stop delay is disabled. table 19. watch-dog timer mode registerwdtmr 0fh/r15: write only bit d7 d6 d5 d4 d3 d2 d1 d0 r/w wwww w www reset xxx0 1 101 note: r = read, w = write, x = indeterminate. bit/ field bit position r/w state description d7Cd5 reserved wx reservedmust be 0 d4 x in w0 xin/int rc select for wdt 0: on-board rc 1: crystal d3 wdt w1 wdt during stop d2 wdt w1 wdt during halt d1Cd0 wdt tap w01 wdt tap int rc osc system clock 00: 3.5 ms 128 sclk 01: 10.0 ms 256 sclk 10: 14.0 ms 512 sclk 11: 56.0 ms 2048 sclk note: not used in conjunction with smr source. note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 47 wdt time select (d0,d1). selects the wdt time period and is con?gured as indi- cated in table 20. wdtmr during halt (d2). this bit determines whether or not the wdt is active during halt mode. a 1 indicates active during halt. the default is 1. wdtmr during stop (d3). this bit determines whether or not the wdt is active during stop mode. because the crystal clock is stopped during stop mode, the on-board rc must be selected as the clock source to the por counter. a 1 indicates active during stop. the default is 1. if the permanent wdt programming option is selected, the wdt runs in all modes and cannot be stopped or disabled if the on board rc oscillator is selected as the clock source for wdt . clock source for wdt (d4). this bit determines which oscillator source is used to clock the internal por and wdt counter chain. if the bit is a 1, the internal rc oscillator is bypassed and the por and wdt clock source is driven from the external pin, x in . the default con?guration of this bit is 0 which selects the internal rc oscillator. wdtmr register accessibility. the wdtmr register is accessible only during the ?rst 64 internal system clock cycles from the execution of the ?rst instruction after power-on reset, watch-dog reset, or stop-mode recovery. after this point, the register cannot be modi?ed by any means, intentional or otherwise. the wdtmr cannot be read and is located in bank fh of the expanded register file at address location 0fh (figure 22). the wdt is permanently enabled (automatically enabled after reset ) through a programmable option. the option is selected when the device is programmed. in this mode, wdt is always activated when the device comes out of reset . execution of the wdt instruction serves to refresh the wdt time-out period. wdt operation in the halt and stop modes is controlled by wdtmr programming. if this option is not selected when the table 20. wdt time select d1 d0 timeout of internal rc osc timeout of system clock 0 0 3.5 ms min 128 sclk 0 1 7 ms min 256 sclk 1 0 14 ms min 512 sclk 1 1 56 ms min 2048 sclk note: sclk = system bus clock cycle. the default on reset is 7 ms. values provided are for v cc = 5.0v. note: note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 48 device is programmed, the wdt must be activated by the user through the wdt instruction and is always disabled by any reset to the device. voltage comparator low-voltage protection. an onboard voltage comparator checks that v cc is at the required level to ensure correct operation of the device. reset is globally driven if v cc is below the speci?ed voltage (low-voltage protection). the minimum oper- ating voltage varies with the temperature and operating frequency, while the low- voltage protection (v lv ) varies with temperature only. the low-voltage protection trip voltage (v lv ) is less than 3v and more than 1.4v under the following conditions. the device functions normally at or above 4.5v under all conditions. below 4.5v, the device functions normally until the low-voltage protection trip point (v lv ) is reached, for the temperatures and operating frequencies in case 1 and case 2, in table 21. the device is guaranteed to function normally at supply voltages above figure 22. resets and watch-dog timer example clk 18 clock reset generator reset clear wdt tap select internal rc osc. ck clr 5ms por 5ms 15ms 25ms 100ms 2v operating voltage det. internal reset wdt select (wdtmr) clk source select (wdtmr) xtal v v from stop mode recovery source wdt stop delay select (smr) + 4 clock filter wdt/por counter chain m u x reset dd lv
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary functional description 49 the low-voltage protection trip point. the actual low-voltage protection trip point is a function of temperature and process parameters (figure 23). the internal clock frequency relationship to the crystal clock is dependent on smr bit 0 1 setting. figure 23. typical low-voltage protection vs. temperature table 21. maximum (v lv ) conditions: case 1: t a = C40oc, +105oc, internal clock frequency equal or less than 4 mhz case 2: t a = C40oc, +85oc, internal clock frequency equal or less than 6 mhz v cc (volts) 3.60 3.20 3.00 2.80 2.60 2.40 -60 -40 -20 0 20 40 60 80 100 120 140 3.80 3.40 temperature ( c) v (typical) lv a b a b run/halt mode stop mode note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 50 control registers the muze family of z8 parts offers 3 banks of registers, including eight asci reg- isters in bank ah , as detailed in the following pages. expanded register file, bank 0h bank 0h of the expanded register file contains 15 registers that perform the timer, prescaler, port, interrupt, flag, and pointer functions, as shown in tables 23 through 37. these 15 registers are not reset by a stop-mode recovery. table 22 lists the reset states of all 15 bank 0h registers. table 22. expanded register file registersreset states d7 d6 d5 d4 d3 d2 d1 d0 f0h reserved f1h tmr* 00000000 f2h t1* xxxxxxxx f3h pre1* xxxxxx0 0 f4h t0* xxxxxxxx f5h pre0* xxxxxxx0 f6h p2m* 11111111 f7h p3m* 00000000 f8h p01m* 01001101 f9h ipr* xxxxxxxx fah irq* 00000000 fbh imr* 0xxxxxxx fch flags* xxxxxxxx fdh rp* 00000000 feh sph* 00000000 ffh spl* 00000000 note: *not reset with a stop-mode recovery.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 51 timer mode register the timer mode register, tmr, controls timing and counter functions. read/ write and reset states for bits d7Cd0 are listed in table 23. table 23. timer mode registertmr f1h/r241 bank 0h: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset state 0000 0 000 note: r = read, w = write. bit position bit field r/w state description d7Cd6 t out mode r/w 00 t out mode 00: off 01: t0 output 10: t1 output 11: internal clock output d5Cd4 t in mode r/w 00 t in mode 00: external clock input 01: gate input 10: trigger input (nonretriggerable) 11: trigger input (retriggerable) d3 t1 count r/w 0 t1 count 0: disable 1: enable d2 t1 r/w 0 t1 0: no function 1: load t1 d1 t0 count r/w 0 t0 count 0: disable 1: enable d0 t0 r/w 0 t0 0: no function 1: load t0
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 52 counter/timer 1 register the counter/timer 1 register, t1, controls timing and counter functions. read/ write and reset states for bits d7Cd0 are listed in table 24. prescaler 1 register the prescaler 1 register, pre1, controls clocking functions. read/write and reset states for bits d7Cd0 are listed in table 25. table 24. counter/timer 1 registert1 f2h/r242 bank 0h: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset state xxxx x xxx note: r = read, w = write, x = indeterminate. bit position bit field r/w state description d7Cd0 t1 rx t1 current value wx t1 automatic reload value range = 1C256 decimal; 01hC00h table 25. prescaler 1 registerpre1 f3h/r243 bank 0h: write only bit d7 d6 d5 d4 d3 d2 d1 d0 r/w wwww w www reset state xxx x x x 0 0 note: w = write, x = indeterminate. bit position bit field r/w state description d7Cd2 prescaler wx prescaler modulo range = 1C64 decimal; 01hC00h d1 clock w0 clock source 0: t1 external timing input (t in ) mode 1: t1 internal d0 count w0 count mode 0: t1 single pass 1: t1 modulo n
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 53 counter/timer 0 register the counter/timer 0 register, t0, controls timing and counter functions. read/ write and reset states for bits d7Cd0 are listed in table 26. prescaler 0 register the prescaler 0 register pre0 controls clocking functions. write and reset states for bits d7Cd0 are listed in table 27. table 26. counter/timer 0 registert0 f4h/r244 bank 0h: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset state xxxx x xxx note: r = read, w = write, x = indeterminate. bit position bit field r/w state description d7Cd0 t0 rx t0 current value wx t0 automatic reload value range = 1C256 decimal table 27. prescaler 0 registerpre0 f5h/r245 bank 0h: write only bit d7 d6 d5 d4 d3 d2 d1 d0 r/w wwww w www reset state xxx x x x x 0 note: w = write, x = indeterminate. bit position bit field r/w state description d7Cd2 prescaler wx prescaler modulo range = 1C64 decimal; 01hC00h d1 reserved wx reservedmust be 0 d0 count w0 count mode 0: t0 single pass 1: t0 modulo n
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 54 port 2 mode register the port 2 mode register, p2m, controls port 2 i/o functions. write and reset states for bits d7Cd0 are listed in table 28. port 3 mode register the port 3 mode register p3m controls port 3 i/o functions. write and reset states for bits d7Cd0 are listed in table 29. table 28. port 2 mode registerp2m f6h/r246 bank 0h: write only bit d7 d6 d5 d4 d3 d2 d1 d0 r/w wwww w www reset state 1111 1 111 note: w = write. bit position bit field r/w state description d7Cd0 p20Cp27 w1 p20Cp27 i/o definition 0: defines bit as output 1: defines bit as input table 29. port 3 mode registerp3m f7h/r247 bank 0h: write only bit d7 d6 d5 d4 d3 d2 d1 d0 r/w wwww w www reset state 0000 0 000 note: w = write. bit position bit field r/w state description d7Cd6 reserved w00 reservedmust be 00 d5 port 3 w0 port 3 0: p31 = input (t in ) p36 = output (t out ) 1: p31 = dav2 /rdy2 p36 = rdy2/dav2 d4Cd3 port 3 w00 port 3 00: p33 = input; p34 = output 01: p33 = input; p34 = dm 10: p33 = input; p34 = dm 11: p33 = dav1 /rdy1; p34 = rdy1/dav1
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 55 ports 0 and 1 mode register the ports 0 and 1 mode register, p01m, controls port and timing functions for ports 0 and 1. write and reset states for bits d7Cd0 are listed in table 30. d2 port 3 w0 port 3 0: p32 = input; p35 = output 1: p32 = dav0 /rdy0; p35 = rdy0/dav0 d1 port 3 w0 port 3 0: p31, p32 digital mode 1: p31, p32 analog mode d0 port 2 w0 port 2 0: open-drain 1: push-pull table 30. ports 0 and 1 mode registerp01m f8h/r248 bank 0h: write only bit d7 d6 d5 d4 d3 d2 d1 d0 r/w wwww w www reset state 0100 1 101 note: w = write. bit position bit field r/w state description d7Cd6 p04Cp07 w01 p04Cp07 mode* 00: output 01: input 1x: a15Ca12 (z86e14x only) d5 timing w0 external memory timing 0: normal 1: extended d4Cd3 p10Cp17 w01 p10Cp17 mode* 00: byte output 01: byte input 10: ad7Cad0 11: high-impedance ad7Cad0, as , ds , r/ w , a11Ca8, a15Ca12, if selected note: *for 20- and 28-pin devices, the user must set d7=0, d4=0, d2=1, and d1=0. bit position bit field r/w state description
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 56 interrupt priority register the interrupt priority register, ipr, prioritizes interrupt functions. write and reset states for bits d7Cd0 are listed in table 31. d2 stack w1 stack selection* 0: external 1: internal d1Cd0 p00Cp03 w01 p00Cp03 mode* 00: output 01: input 1x: a11Ca8 (z86e14x only) table 31. interrupt priority registeripr f9h/r249 bank 0h: write only bit d7 d6 d5 d4 d3 d2 d1 d0 r/w wwww w www reset state xxxx x xxx note: w = write, x = indeterminate. bit position bit field r/w state description d7Cd6 reserved wxx reservedmust be 0 d5 irq3, irq5 wx irq3, irq5 priority (group a) 0: irq5 > irq3 1: irq3 > irq5 d4,d3,d0 interrupt w xxx interrupt group priority 000: reserved 001: c > a > b 010: a > b > c 011: a > c > b 100: b > c > a 101: c > b > a 110: b > a > c 111: reserved d2 irq0, irq2 wx irq0, irq2 priority (group b) 0: irq2 > irq0 1: irq0 > irq2 bit position bit field r/w state description note: *for 20- and 28-pin devices, the user must set d7=0, d4=0, d2=1, and d1=0.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 57 interrupt request register the interrupt request register, irq, controls interrupt functions. read/write and reset states for bits d7Cd0 are listed in table 32. d1 irq1, irq4 wx irq1, irq4 priority (group c) 0: irq1 > irq4 1: irq4 > irq1 table 32. interrupt request registerirq fah/r250 bank 0h: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0000 0 000 note: r = read, w = write. bit position bit field r/w state description d7Cd6 interrupt edge r/w 00 interrupt edge 00: p31 p32 01: p31 p32 10: p31 p32 11: p31 p32 d5 irq5 r/w 0 interrupt irq5 = t1 0: no interrupt pending 1: interrupt pending d4 irq4 r/w 0 interrupt irq4 = t0 0: no interrupt pending 1: interrupt pending d3 irq3 r/w 0 interrupt irq3 = p30 input/uart 0: no interrupt pending 1: interrupt pending d2 irq2 r/w 0 interrupt irq2 = p31 input 0: no interrupt pending 1: interrupt pending bit position bit field r/w state description
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 58 interrupt mask register the interrupt mask register, imr, controls interrupt functions. read/write and reset states for bits d7Cd0 are listed in table 33. d1 irq1 r/w 0 interrupt irq1 = p33 input 0: no interrupt pending 1: interrupt pending d0 irq0 r/w 0 interrupt irq0 = p32 input 0: no interrupt pending 1: interrupt pending table 33. interrupt mask registerimr fbh/r251 bank 0h: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0xxx x xxx note: r = read, w = write, x = indeterminate. bit position bit field r/w state description d7 mie r/w 0 master interrupt enable 1: enable interrupts 0: disable interrupts d6 ram protect r/w x ram protect 1: enable ram protect 0: disable ram protect d5Cd0 irq5Cirq0 r/w x interrupt request 1: enable irq0Cirq5 0: disable irq0Cirq5 bit position bit field r/w state description
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 59 flags register the cpu sets ?ags in the flags register, flags, to allow the user to perform tests based on differing logical states. read/write and reset states for bits d7C d0 are listed in table 34. register pointer register the register pointer register, rp, controls pointer functions in the working regis- ters. read/write and reset states for bits d7Cd0 are listed in table 35. table 34. flags registerflags fch/r252 bank 0h: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxx x xxx note: r = read, w = write, x = indeterminate. bit position bit field r/w state description d7 carry r/w x carry flag d6 zero r/w x zero flag d5 sign r/w x sign flag d4 overflow r/w x overflow flag d3 decimal adjust r/w x decimal adjust flag d2 half carry r/w x half carry flag d1 user r/w x user flag f2* d0 user r/w x user flag f1* note: *not affected by reset . table 35. register pointerrp fdh/r253 bank 0h: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0000 0 000 note: r = read, w = write. bit position bit field r/w state description d7Cd4 working register pointer r/w 0 working register pointer
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 60 stack pointer high register the stack pointer high register, sph, controls pointer functions in the upper byte. read/write and reset states for bits d7Cd0 are listed in table 36. stack pointer low register the stack pointer low register, spl, controls pointer functions in the lower byte. read/write and reset states for bits d7Cd0 are listed in table 37. d3Cd0 expanded register file bank r/w 0 expanded register file bank table 36. stack pointer highsph feh/r254 bank 0h: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0000 0 000 note: r = read, w = write. bit position bit field r/w state description d7Cd0 sph r/w 0 stack pointer upper byte* (sp15Csp8) note: *this register can be employed as a gpr for 20- and 28-pin devices. table 37. stack pointer lowspl ffh/r255 bank 0h: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0000 0 000 note: r = read, w = write. bit position bit field r/w state description d7Cd0 spl r/w 0 stack pointer lower byte (sp7Csp0) bit position bit field r/w state description
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 61 asci registersexpanded register file, bank ah bank ah of the expanded register file includes registers that perform asci func- tions. the 8 available registers are the transmit data, receive data, multiproces- sor control, extension, time constant, and status registers, as shown in tables 39 through 46. these eight registers are not reset by a stop-mode recovery. an additional register, 09h , is available for general purposes. table 38 lists the reset states of all 16 asci registers. table 38. expanded register file registersreset states d7 d6 d5 d4 d3 d2 d1 d0 00h reserved 01h* tdr xxxxxxxx 02h* rdr xxxxxxxx 03h* cntla 00010000 04h* cntlb 00000111 05h* asext p300000010 06h* astl 11111111 07h* asth 11111111 08h* stat 00000000 09h general-purpose 0ah reserved 0bh reserved 0ch reserved 0dh reserved 0eh reserved 0fh reserved note: *not reset with a stop-mode recovery.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 62 transmit data register the transmit data register, tdr, monitors data transmission functions in the fifo. read/write and reset states for bits d7Cd0 are listed in table 39. receive data register the receive data register, rdr, monitors data receive functions in the fifo. read/write and reset states for bits d7Cd0 are listed in table 40. table 39. transmit data registertdr 01h/r1 bank ah: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxx x xxx note: r = read, w = write, x = indeterminate. bit position bit field r/w state description d7Cd0 tdr r/w x transmit data register table 40. receive data registerrdr 02h/r2 bank ah : read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxx x xxx note: r = read, w = write, x = indeterminate. bit position bit field r/w state description d7Cd0 rdr r/w x receive data register
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 63 control register a control register a, cntla, controls data transmit, receive, and clocking func- tions. read/write and reset states for bits d7Cd0 are listed in table 41. table 41. control register acntla 03h/r3 bank ah: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0001 0 000 note: r = read, w = write. bit position bit field r/w state description d7 mpe r/w 0 multiprocessor enable 0: receive all bytes 1: filter bytes with mpb = 0 d6 re r/w 0 receiver enable 0: asci receiver disabled (p30 = input) 1: asci receiver enabled (p30 = rx) d5 te r/w 0 transmitter enable 0: asci transmitter disabled (p37 = output) 1: asci transmitter enabled (p37 = tx) d4 reserved r/w 1 reserved d3 mpbr r0 multiprocessor bit received efr w error flag reset 0: clear error latches 1: no effect d2Cd0 mod2C0 r0 mode select mod2number of data bits 0: 7 data bits 1: 8 data bits mode select mod1parity enabled 0: no parity 1: with parity mode select mod0number of stop bits 0: 1 stop bit 1: 2 stop bits
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 64 control register b control register b, cntlb, controls multiprocessor, parity, and clock sourcing functions. read/write and reset states for bits d7Cd0 are listed in table 42. table 42. control register bcntlb 04h/r4 bank ah: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0000 0 111 note: r = read, w = write. bit position bit field r/w state description d7 mpbt r/w 0 multiprocessor bit transmitter 0: transmit 0 in mpb 1: transmit 1 in mpb d6 mp r/w 0 multiprocessor mode 0: multiprocessor mode disabled 1: multiprocessor mode enabled (no parity) d5 pr w0 prescale 0: brg 10 1: brg 30 d4 peo r/w 0 parity even/odd 0: even parity 1: odd parity d3 dr r/w 0 divide ratio 0: divide by 16 1: divide by 64 d2 ss2 r1 clock source and speed bits ss2 0: 1, 2, 4, 8 1: 16, 32, 64, reserved d1 ss1 r1 clock source and speed bits ss1 0: 1, 2, 16, 32 1: 4, 8, 64, reserved d0 ss0 r1 clock source and speed bits ss0 0: 1, 4, 16, 64 1: 2, 8, 32, reserved
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 65 asci extension control register the asci extension control register, asext, controls asci transmission func- tions. read/write and reset states for bits d7Cd0 are listed in table 43. table 43. extension control registerasext 05h/r5 bank ah: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r r/w r/w r/w r/w r/w r r/w reset x000 0 010 note: r = read, w = write. bit position bit field r/w state description d7 rx rx rx data state d6 reserved r/w 0 reserved d5 reserved r/w 0 reserved d4 reserved r/w 0 reserved (must be 0) d3 brg r/w 0 baud rate generator mode 0: use ss selection 1: use asth or astl value d2 ris r/w 0 rx interrupt on start bit 0: no irq on start bit 1: irq3 on start bit d1 bd r1 break detect 0: valid data byte 1: break detected d0 sb r/w 0 send break 0: normal operation 1: send break
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 66 asci time constant low register the asci time constant low register, astl, controls transmission functions in the lower byte. read/write and reset states for bits d7Cd0 are listed in table 44. asci time constant high register the asci time constant high register, asth, controls transmission functions in the upper byte. read/write and reset states for bits d7Cd0 are listed in table 45. table 44. time constant low registerastl 06h/r6 bank ah: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1111 1 111 note: r = read, w = write. bit position bit field r/w state description d7Cd0 astl r/w 1 asci time constant low table 45. time constant register highasth 07h/r7 bank ah: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1111 1 111 note: r = read, w = write. bit position bit field r/w state description d7Cd0 asth r/w 1 asci time constant high
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 67 asci status register the asci status register, s tat, controls status functions. read/write and reset states for bits d7Cd0 are listed in table 46. expanded register file, bank fh expanded register file fh bank 0h contains 5 registers that perform the port con?guration, verify, stop-mode recovery, and watch-dog timer mode func- tions, as shown in tables 49 through 52. these 5 registers are not reset by a stop-mode recovery. table 47 lists the reset states of all 5 bank 0h registers. table 46. status registerstat 08h/r8 bank ah: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r/wr/wrr/w reset 0000 0 000 note: r = read, w = write. bit position bit field r/w state description d7 rdrne r0 receive data register not empty 0: receive fifo empty 1: receive fifo contains 1 or more bytes d6 oe r0 overrun error 0: receive ok 1: next byte is a fifo overrun d5 pe r0 parity error 0: parity ok 1: parity error d4 fe r0 framing error 0: receive ok 1: framing error d3 rie r/w 0 receive interrupt enable 0: no irq on receive 1: enable receiver interrupt d2 reserved r/w 0 reserved d1 tdre r0 transmit data register empty 0: transmitter working 1: transmit buffer empty d0 tie r/w 0 transmit interrupt enable 0: no irq on transmit 1: irq3 on tdre
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 68 table 47. expanded register file registersreset states d7 d6 d5 d4 d3 d2 d1 d0 00h pcon* 11111110 01h reserved 02h reserved 03h reserved 04h reserved 05h reserved 06h reserved 07h reserved 08h reserved 09h reserved 0ah reserved 0bh smr* 00100000 0ch reserved 0dh smr2* xxxxxx0 0 0eh reserved 0fh wdtmr* xxx01101 note: *not reset with a stop-mode recovery.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 69 port con?guration register the port con?guration register, pcon, controls the con?gurations of ports 0, 1, 2, and 3. write and reset states for bits d7Cd0 are listed in table 48. table 48. port con?guration registerpcon 00h/r0 bank fh: write only bit d7 d6 d5 d4 d3 d2 d1 d0 r/w wwww w www reset 1111 1 110 note: w = write. bit position bit field r/w state description d7 oscillator w 1 low-emi oscillator 0: low emi 1: standard d6 port 3 i/o w 1 port 3 0: low emi 1: standard d5 port 2 i/o w 1 port 2 0: low emi 1: standard d4 port 1 i/o w 1 port 1* 0: low emi 1: standard d3 port 0 i/o w 1 port 0? 0: low emi 1: standard d2 port 0 i/o w 1 port 0 0: open-drain 1: push-pull active d1 port 1 i/o w 1 port 1 * ? 0: open-drain 1: push-pull active d0 port 3 w 0 port 3 comparator output 0: p34, p37 standard output 1: p34, p37 comparator output notes: 1. must be set to 1 when using an emulator. 2. must be set to 1 for both 20- and 28-pin devices.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 70 verify register the verify register, vfy, is only available after the icsp unlock sequence exe- cutes. read and reset states for bits d7Cd0 are listed in table 49. for more infor- mation on the vfy register, please see the muze prog r amming speci? cation . stop-mode recovery register the stop-mode recovery register, smr, controls clocking functions. read/ write and reset states for bits d7Cd0 are listed in table 50. table 49. verify registervfy 09h/r09 bank fh: read only bit d7 d6 d5 d4 d3 d2 d1 d0 r/w rrrr r rrr reset xxxx x xxx note: r = read, x = indeterminate. bit position bit field r/w state description d7Cd2 reserved rx reserved d1 vfy1 rx verify 1 programming verification result is output at this register d0 vfy0 rx verify 0 programming verification result is output at this register table 50. stop-mode recovery registersmr 0bh/r11 bank fh:read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w rwww w www reset 0010 0 000 note: r = read, w = write. bit position bit field r/w state description d7 stop r0 stop flag 0: por 1: stop recovery notes: 1. for the stop-mode recovery source, either smr or smr2 can be selected. if smr is used to select the stop-mode recovery source, bits d1Cd0 of smr2 must be 0. 2. cleared by reset and smr.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 71 d6 stop-mode recovery w0 stop-mode recovery level 0: low 1: high d5 stop delay w1 stop delay 0: off 1: on d4Cd2 stop mode w 000 stop-mode recovery source* 000: por only and/or external reset 001: p30 010: p31 011: p32 100: p33 101: p27 110: p2 nor 0C3 111: p2 nor 0C7 d1 clock w0 external clock divide-by-2 0: sclk tclk = crystal 2 1: sclk = crystal d0 sclk/tclk w0 sclk/tclk divide-by-16 0: off 1: on bit position bit field r/w state description notes: 1. for the stop-mode recovery source, either smr or smr2 can be selected. if smr is used to select the stop-mode recovery source, bits d1Cd0 of smr2 must be 0. 2. cleared by reset and smr.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 72 stop-mode recovery register 2 the stop-mode recovery register, smr2, controls additional port 2 clocking functions. write and reset states for bits d7Cd0 are listed in table 51. watch-dog timer mode register the watch-dog timer mode register, wdtmr, controls watch-dog timer func- tions. write and reset states for bits d7Cd0 are listed in table 52. table 51. stop-mode recovery register 2smr2 0dh/r13 bank fh: write only bit d7 d6 d5 d4 d3 d2 d1 d0 r/w wwww w www reset xxx x x x 0 0 note: w = write, x = indeterminate. bit position bit field r/w state description d7Cd2 reserved wx reservedmust be 0 d1Cd0 stop mode w00 stop-mode recovery source 2* 00: por only 01: and p20, p21, p22, p23 10: and p20, p21, p22, p23, p24, p25, p26, p27 note: for the stop-mode recovery source, either smr or smr2 can be selected. if smr2 is used to select the stop-mode recovery source, bits d4Cd2 of smr must be 0. table 52. watch-dog timer mode registerwdtmr 0fh/r15 bank fh: write only bit d7 d6 d5 d4 d3 d2 d1 d0 r/w wwww w www reset xxx0 1 101 note: w = write, x = indeterminate. bit position bit field r/w state description d7Cd5 reserved wx reservedmust be 0 d4 x in w0 crystal input /internal rc select for wdt 0: on-board rc 1: crystal note: not used in conjunction with smr source.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary control registers 73 d3 wdt w1 wdt during stop 0: wdt disabled during stop mode 1: wdt enabled during stop mode d2 wdt w1 wdt during halt 0: wdt disabled during halt mode 1: wdt enabled during halt mode d1Cd0 wdt tap w01 wdt tap int. rc osc. system clock 00: 3.5 ms 128 sclk 01: 7 ms 256 sclk 10: 14 ms 512 sclk 11: 56 ms 2048 sclk bit position bit field r/w state description note: not used in conjunction with smr source.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary int errupts 74 interrupts interrupt block diagram figure 24. interrupt block diagram interrupt edge select irq (d6, d7) irq1, 3, 4, 5 irq imr ipr priority logic 6 global interrupt enable vector select interrupt request irq0 irq2
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 75 electrical characteristics absolute maximum ratings stresses greater than the absolute maximum ratings listed in table 53 may cause permanent damage to the device. this rating is a stress rating only. func- tional operation of the device at any condition above those indicated in the opera- tional sections of these speci?cations is not implied. exposure to absolute maximum rating conditions for an extended period may affect device reliability. total power dissipation should not exceed 1.21 w for the package. power dissipa- tion is calculated as follows: table 53. absolute maximum ratings parameter min max units notes ambient temperature under bias C40 +105 c storage temperature C65 +150 c voltage on any pin with respect to v ss C0.6 +7 v 1 voltage on v dd pin with respect to v ss C0.3 +7 v voltage on x in and reset pins with respect to v ss C0.6 v dd +1 v 2 total power dissipation 1.21 w maximum allowable current out of v ss 220 ma maximum allowable current into v dd 180 ma maximum allowable current into an input pin C600 +600 a 3 maximum allowable current into an open-drain pin C600 +600 a 4 maximum allowable output current sunk by any i/o pin 25 ma maximum allowable output current sourced by any i/o pin 25 ma notes: 1. applies to all pins except crystal pins and where otherwise noted. 2. there is no input protection diode from pin to v dd and current into pin is limited to 600 a. 3. excludes crystal pins. 4. device pin is not at an output low state. total power dissipation = v dd x [i dd C (sum of i oh ), + sum of [(v dd C v oh ) x i oh ] + sum of (v ol x i ol )
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 76 dc electrical characteristics standard temperature range table 54. dc electrical characteristics at standard temperature sym parameter v cc1 t a = 0c to +70c typical 2 @25c units conditions notes min max v ch clock input high voltage 4.5v 0.7 v cc v cc +0.3 1.8 v driven by external clock generator 5.5v 0.7 v cc v cc +0.3 2.6 v driven by external clock generator v cl clock input low voltage 4.5v gndC0.3 0.2 v cc 1.2 v driven by external clock generator 5.5v gndC0.3 0.2 v cc 2.1 v driven by external clock generator v ih input high voltage 4.5v 0.7 v cc v cc +0.3 1.8 v 5.5v 0.7 v cc v cc +0.3 2.6 v v il input low voltage 4.5v gndC0.3 0.2 v cc 1.1 v 5.5v gndC0.3 0.2 v cc 1.6 v notes: 1. the v cc voltage speci?cation of 4.5v guarantees 3.3v 0.3v with typicals at v cc = 3.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v with typicals at v cc = 5.0v. 2. typical voltage is v cc = 5.0v and 3.3v. 3. standard mode (not low-emi mode). 4. not applicable to devices in 28-pin packages. 5. for analog comparator, inputs when analog comparators are enabled. 6. all outputs unloaded, i/o pins ?oating, inputs at rail. 7. same as note 6, except inputs at v cc . 8. clock must be forced low, when x in is clock-driven and x out is ?oating. 9. 0oc to 70oc (standard temperature). 10.autolatch (mask option) selected. 11.the v lv voltage increases as the temperature decreases and overlaps lower v cc operating region. see figure 23 on page 49 12.C40?c to 150?c (extended temperature).
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 77 v oh output high voltage (low-emi mode) 4.5v v cc C0.4 3.1 v i oh = C0.5 ma 5.0v v cc C0.4 4.8 v i oh = C0.5 ma v oh1 output high voltage 4.5v v cc C0.4 3.1 v i oh = C2.0 ma 3 5.5v v cc C0.4 4.8 v i oh = C2.0 ma 3 v ol output low voltage (low-emi mode) 4.5v 0.6 0.2 v i ol = 1.0 ma 5.0v 0.4 0.1 v i ol = 1.0 ma v ol1 output low voltage 4.5v 0.6 0.2 v i ol = +4.0 ma 3 5.5v 0.4 0.1 v i ol = +4.0 ma 3 v ol2 output low voltage 4.5v 1.2 0.3 v i ol = +6 ma 3 5.5v 1.2 0.4 v i ol = +12 ma 3 v rh reset input high voltage 4.5v 0.8 v cc v cc 1.8 v 4 5.5v 0.8 v cc v cc 2.6 v 4 v rl reset input low voltage 4.5v gndC0.3 0.2 v cc 1.1 v 4 5.5v gndC0.3 0.2 v cc 1.6 v 4 v olr reset output low voltage 4.5v 0.6 0.3 v i ol = +1.0 ma 4 5.5v 0.6 0.3 v i ol = +1.0 ma 4 table 54. dc electrical characteristics at standard temperature (continued) sym parameter v cc1 t a = 0c to +70c typical 2 @25c units conditions notes min max notes: 1. the v cc voltage speci?cation of 4.5v guarantees 3.3v 0.3v with typicals at v cc = 3.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v with typicals at v cc = 5.0v. 2. typical voltage is v cc = 5.0v and 3.3v. 3. standard mode (not low-emi mode). 4. not applicable to devices in 28-pin packages. 5. for analog comparator, inputs when analog comparators are enabled. 6. all outputs unloaded, i/o pins ?oating, inputs at rail. 7. same as note 6, except inputs at v cc . 8. clock must be forced low, when x in is clock-driven and x out is ?oating. 9. 0oc to 70oc (standard temperature). 10.autolatch (mask option) selected. 11.the v lv voltage increases as the temperature decreases and overlaps lower v cc operating region. see figure 23 on page 49 12.C40?c to 150?c (extended temperature).
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 78 v offset comparator input offset voltage 4.5v 25 10 mv 5 5.5v 25 10 mv 5 i il input leakage 4.5v C1 2 0.004 a v in = 0v, v cc 5.5v C1 2 0.004 a v in = 0v, v cc i ol output leakage 4.5v C1 1 0.004 a v in = 0v, v cc 5.5v C1 1 0.004 a v in = 0v, v cc i ir reset input current 4.5v C20 C130 C60 a 5.5v C20 C180 C85 a i cc supply current 4.5v 20 7 ma @ 16 mhz 6 5.5v 25 20 ma @ 16 mhz 6 4.5v 15 5 ma @ 12 mhz 6 5.5v 20 15 ma @ 12 mhz 6 table 54. dc electrical characteristics at standard temperature (continued) sym parameter v cc1 t a = 0c to +70c typical 2 @25c units conditions notes min max notes: 1. the v cc voltage speci?cation of 4.5v guarantees 3.3v 0.3v with typicals at v cc = 3.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v with typicals at v cc = 5.0v. 2. typical voltage is v cc = 5.0v and 3.3v. 3. standard mode (not low-emi mode). 4. not applicable to devices in 28-pin packages. 5. for analog comparator, inputs when analog comparators are enabled. 6. all outputs unloaded, i/o pins ?oating, inputs at rail. 7. same as note 6, except inputs at v cc . 8. clock must be forced low, when x in is clock-driven and x out is ?oating. 9. 0oc to 70oc (standard temperature). 10.autolatch (mask option) selected. 11.the v lv voltage increases as the temperature decreases and overlaps lower v cc operating region. see figure 23 on page 49 12.C40?c to 150?c (extended temperature).
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 79 i cc1 standby current (halt mode) 4.5v 4.5 2.0 ma v in = 0v, v cc @ 16 mhz 6 5.5v 8 3.7 ma v in = 0v, v cc @ 16 mhz 6 4.5v 3.4 1.5 ma clock divide- by-16 @ 16 mhz 6 5.5v 7.0 2.9 ma clock divide- by-16 @ 16 mhz 6 i cc2 standby current (stop mode) 4.5v 8 2 a v in = 0v, v cc wdt is not running 7,8 5.5v 10 4 a v in = 0v, v cc wdt is not running 7,8 4.5v 500 310 a v in = 0v, v cc wdt is running 7,8,9 5.5v 800 600 a v in = 0v, v cc wdt is running 7,8,9 table 54. dc electrical characteristics at standard temperature (continued) sym parameter v cc1 t a = 0c to +70c typical 2 @25c units conditions notes min max notes: 1. the v cc voltage speci?cation of 4.5v guarantees 3.3v 0.3v with typicals at v cc = 3.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v with typicals at v cc = 5.0v. 2. typical voltage is v cc = 5.0v and 3.3v. 3. standard mode (not low-emi mode). 4. not applicable to devices in 28-pin packages. 5. for analog comparator, inputs when analog comparators are enabled. 6. all outputs unloaded, i/o pins ?oating, inputs at rail. 7. same as note 6, except inputs at v cc . 8. clock must be forced low, when x in is clock-driven and x out is ?oating. 9. 0oc to 70oc (standard temperature). 10.autolatch (mask option) selected. 11.the v lv voltage increases as the temperature decreases and overlaps lower v cc operating region. see figure 23 on page 49 12.C40?c to 150?c (extended temperature).
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 80 v icr input common mode voltage range 4.5v 0 v cc C1.0v v 5 5.5v 0 v cc C1.0v v 5 i all autolatch low current 4.5v 0.7 8 3 a 0v z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 81 extended temperature range table 55. dc electrical characteristics at extended temperature sym parameter v cc1 t a = C40c to +105c typical 2 @25c units conditions notes min max v ch clock input high voltage 4.5v 0.7 v cc v cc +0.3 1.8 v driven by external clock generator 5.5v 0.7 v cc v cc +0.3 2.6 v driven by external clock generator v cl clock input low voltage 4.5v gndC0.3 0.2 v cc 1.2 v driven by external clock generator 5.5v gndC0.3 0.2 v cc 2.1 v driven by external clock generator v ih input high voltage 4.5v 0.7 v cc v cc +0.3 1.8 v 5.5v 0.7 v cc v cc +0.3 2.6 v v il input low voltage 4.5v gndC0.3 0.2 v cc 1.1 v 5.5v gndC0.3 0.2 v cc 1.6 v v oh output high voltage (low-emi mode) 4.5v v cc C0.4 3.1 v i oh = C0.5 ma 5.0v v cc C0.4 4.8 v i oh = C0.5 ma v oh1 output high voltage 4.5v v cc C0.4 3.1 v i oh = C2.0 ma 3 5.5v v cc C0.4 4.8 v i oh = C2.0 ma 3 notes: 1. the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v with typicals at v cc = 5.0v. 2. typicals are at v cc = 5.0v and 3.3v. 3. standard mode (not low emi). 4. not applicable to devices in 28-pin packages. 5. for analog comparator, inputs when analog comparators are enabled. 6. all outputs unloaded, i/o pins floating, inputs at rail. 7. same as note 6, except inputs at v cc . 8. clock must be forced low, when x in is clock-driven and x out is floating. 9. 0oc to 70oc (standard temperature). 10. autolatch (mask option) selected. 11. the v lv voltage increases as the temperature decreases and overlaps lower v cc operating region. 12. C40?c to 150?c (extended temperature).
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 82 v ol output low voltage (low-emi mode) 4.5v 0.6 0.2 v i ol = 1.0 ma 5.0v 0.4 0.1 v i ol = 1.0 ma v ol1 output low voltage 4.5v 0.6 0.2 v i ol = +4.0 ma 3 5.5v 0.4 0.1 v i ol = +4.0 ma 3 v ol2 output low voltage 4.5v 1.2 0.3 v i ol = +6 ma 3 5.5v 1.2 0.4 v i ol = +12 ma 3 v rh reset input high voltage 4.5v 0.8 v cc v cc 1.8 v 4 5.5v 0.8 v cc v cc 2.6 v 4 v rl reset input low voltage 4.5v gndC0.3 0.2 v cc 1.1 v 4 5.5v gndC0.3 0.2 v cc 1.6 v 4 v olr reset output low voltage 4.5v 0.6 0.3 v i ol = +1.0 ma 4 5.5v 0.6 0.3 v i ol = +1.0 ma 4 v offset comparator input offset voltage 4.5v 25 10 mv 5 5.5v 25 10 mv 5 i il input leakage 4.5v C1 2 0.004 a v in = 0v, v cc 5.5v C1 2 0.004 a v in = 0v, v cc i ol output leakage 4.5v C1 2 0.004 a v in = 0v, v cc 5.5v C1 2 0.004 a v in = 0v, v cc table 55. dc electrical characteristics at extended temperature (continued) sym parameter v cc1 t a = C40c to +105c typical 2 @25c units conditions notes min max notes: 1. the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v with typicals at v cc = 5.0v. 2. typicals are at v cc = 5.0v and 3.3v. 3. standard mode (not low emi). 4. not applicable to devices in 28-pin packages. 5. for analog comparator, inputs when analog comparators are enabled. 6. all outputs unloaded, i/o pins floating, inputs at rail. 7. same as note 6, except inputs at v cc . 8. clock must be forced low, when x in is clock-driven and x out is floating. 9. 0oc to 70oc (standard temperature). 10. autolatch (mask option) selected. 11. the v lv voltage increases as the temperature decreases and overlaps lower v cc operating region. 12. C40?c to 150?c (extended temperature).
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 83 i ir reset input current 4.5v C18 C130 C60 a 5.5v C18 C180 C85 a i cc supply current 4.5v 20 7 ma @ 16 mhz 6 5.5v 25 20 ma @ 16 mhz 6 4.5v 15 5 ma @ 12 mhz 6 5.5v 20 15 ma @ 12 mhz 6 i cc1 standby current (halt mode) 4.5v 4.5 2.0 ma v in = 0v, v cc @ 16 mhz 6 5.5v 8 3.7 ma v in = 0v, v cc @ 16 mhz 6 4.5v 3.4 1.5 ma clock divide- by-16 @ 16 mhz 6 5.5v 7.0 2.9 ma clock divide- by-16 @ 16 mhz 6 table 55. dc electrical characteristics at extended temperature (continued) sym parameter v cc1 t a = C40c to +105c typical 2 @25c units conditions notes min max notes: 1. the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v with typicals at v cc = 5.0v. 2. typicals are at v cc = 5.0v and 3.3v. 3. standard mode (not low emi). 4. not applicable to devices in 28-pin packages. 5. for analog comparator, inputs when analog comparators are enabled. 6. all outputs unloaded, i/o pins floating, inputs at rail. 7. same as note 6, except inputs at v cc . 8. clock must be forced low, when x in is clock-driven and x out is floating. 9. 0oc to 70oc (standard temperature). 10. autolatch (mask option) selected. 11. the v lv voltage increases as the temperature decreases and overlaps lower v cc operating region. 12. C40?c to 150?c (extended temperature).
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 84 i cc2 standby current (stop mode) 4.5v 8 2 a v in = 0v, v cc wdt is not running 7,8 5.5v 10 4 a v in = 0v, v cc wdt is not running 7,8 4.5v 600 310 a v in = 0v, v cc wdt is running 7,8,9 5.5v 1000 600 a v in = 0v, v cc wdt is running 7,8,9 v icr input common mode voltage range 4.5v 0 v cc C1.5v v 5 5.5v 0 v cc C1.5v v 5 i all autolatch low current 4.5v 0.7 10 3 a 0v z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 85 i alh autolatch high current 4.5v C0.6 C7 C3 a 0v z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 86 ac electrical characteristics figure 25 illustrates the timing characteristics of the muze family of parts with respect to external input/output sources. see tables 56 and 57 for descriptions of the numbered timing parameters in the ?gure. figure 25. external i/o or memory read and write timing r/w 9 12 18 3 16 13 4 5 8 11 6 17 10 15 7 14 2 1 port 0, dm port 1 as ds (read) port1 ds (write) d7 d0 in d7 d0 out a7 a0 a7 a0 19 20
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 87 standard temperature range table 56. external i/o or memory read and write timingstandard temperature no symbol parameter v cc 1 t a = C0oc to 70oc @ 12 mhz units notes min max 1t d a(as) address valid to as rise delay 4.5v 35 ns 2 5.5v 35 ns 2 2t d as(a) as rise to address float delay 4.5v 45 ns 2 5.5v 45 ns 2 3t d as(dr) as rise to read data reqd valid 4.5v 250 ns 2,3 5.5v 250 ns 2 4t w as as low width 4.5v 55 ns 2 5.5v 55 ns 2 5t d as(ds) address float to ds fall 4.5v 0 ns 5.5v 0 ns 6t w dsr ds (read) low width 4.5v 200 ns 2,3 5.5v 200 ns 2,3 7t w dsw ds (write) low width 4.5v 110 ns 2,3 5.5v 110 ns 2,3 8t d dsr(dr) ds fall to read data reqd valid 4.5v 150 ns 2,3 5.5v 150 ns 2,3 9t h dr(ds) read data to ds rise hold time 4.5v 0 ns 2 5.5v 0 ns 2 10 t d ds(a) ds rise to address active delay 4.5v 45 ns 2 5.5v 55 ns 2 11 t d ds(as) ds rise to as fall delay 4.5v 30 ns 2 5.5v 45 ns 2 12 t d r/w(as) r/w valid to as rise delay 4.5v 45 ns 2 5.5v 45 ns 2 notes: 1. z86e142/e143/e144/e145/e146 only; sclk tclk = crystal 2. 2. the v cc voltage specification of 5.5v guarantees 5.0v 0.5v. 3. timing numbers provided are for minimum t p c.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 88 13 t d ds(r/w) ds rise to r/w not valid 4.5v 45 ns 2 5.5v 45 ns 2 14 t d dw(dsw) write data valid to ds fall (write) delay 4.5v 55 ns 2 5.5v 55 ns 2 15 t d ds(dw) ds rise to write data not valid delay 4.5v 45 ns 2 5.5v 45 ns 2 16 t d a(dr) address valid to read data reqd valid 4.5v 310 ns 2,3 5.5v 310 ns 2,3 17 t d as(ds) as rise to ds fall delay 4.5v 65 ns 2 5.5v 65 ns 2 18 t d dm(as) dm valid to as fall delay 4.5v 35 ns 2 5.5v 35 ns 2 19 t d ds(dm) ds rise to dm valid delay 4.5v 45 ns 2 5.5v 45 ns 2 20 t h ds(as) ds valid to address valid hold time 4.5v 45 ns 2 5.5v 45 ns 2 table 56. external i/o or memory read and write timingstandard temperature (continued) no symbol parameter v cc 1 t a = C0oc to 70oc @ 12 mhz units notes min max notes: 1. z86e142/e143/e144/e145/e146 only; sclk tclk = crystal 2. 2. the v cc voltage specification of 5.5v guarantees 5.0v 0.5v. 3. timing numbers provided are for minimum t p c.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 89 extended temperature range table 57. external i/o or memory read and write timingextended temperature no symbol parameter v cc 1 t a = C40oc to +105oc @ 12 mhz units notes min max 1t d a(as) address valid to as rise delay 4.5v 35 ns 2 5.5v 35 ns 2 2t d as(a) as rise to address float delay 4.5v 45 ns 2 5.5v 45 ns 2 3t d as(dr) as rise to read data reqd valid 4.5v 250 ns 2,3 5.5v 250 ns 2 4t w as as low width 4.5v 55 ns 2 5.5v 55 ns 2 5t d as(ds) address float to ds fall 4.5v 0 ns 5.5v 0 ns 6t w dsr ds (read) low width 4.5v 200 ns 2,3 5.5v 200 ns 2,3 7t w dsw ds (write) low width 4.5v 110 ns 2,3 5.5v 110 ns 2,3 8t d dsr(dr) ds fall to read data reqd valid 4.5v 150 ns 2,3 5.5v 150 ns 2,3 9t h dr(ds) read data to ds rise hold time 4.5v 0 ns 2 5.5v 0 ns 2 10 t d ds(a) ds rise to address active delay 4.5v 45 ns 2 5.5v 55 ns 2 11 t d ds(as) ds rise to as fall delay 4.5v 30 ns 2 5.5v 45 ns 2 notes: 1. e142/e143/e144/e145/e146 only; sclk tclk = crystal 2. 2. the v cc voltage specification of 4.5v guarantees 3.3v 0.3v, and the v cc voltage specification of 5.5v guar- antees 5.0v 0.5v. 3. timing numbers provided are for minimum t p c.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 90 12 t d r/w(as) r/w valid to as rise delay 4.5v 45 ns 2 5.5v 45 ns 2 13 t d ds(r/w) ds rise to r/w not valid 4.5v 45 ns 2 5.5v 45 ns 2 14 t d dw(dsw) write data valid to ds fall (write) delay 4.5v 55 ns 2 5.5v 55 ns 2 15 t d ds(dw) ds rise to write data not valid delay 4.5v 45 ns 2 5.5v 45 ns 2 16 t d a(dr) address valid to read data reqd valid 4.5v 310 ns 2,3 5.5v 310 ns 2,3 17 t d as(ds) as rise to ds fall delay 4.5v 65 ns 2 5.5v 65 ns 2 18 t d dm(as) dm valid to as fall delay 4.5v 35 ns 2 5.5v 35 ns 2 19 t d ds(dm) ds rise to dm valid delay 4.5v 45 ns 2 5.5v 45 ns 2 20 t h ds(as) ds valid to address valid hold time 4.5v 45 ns 2 5.5v 45 ns 2 table 57. external i/o or memory read and write timingextended temperature (continued) no symbol parameter v cc 1 t a = C40oc to +105oc @ 12 mhz units notes min max notes: 1. e142/e143/e144/e145/e146 only; sclk tclk = crystal 2. 2. the v cc voltage specification of 4.5v guarantees 3.3v 0.3v, and the v cc voltage specification of 5.5v guar- antees 5.0v 0.5v. 3. timing numbers provided are for minimum t p c.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 91 additional timing figure 26 illustrates the timing characteristics of the muze family of parts with respect to system clock functions. see t ab les 58 and 59 for descriptions of the numbered timing parameters in the ?gure. figure 26. additional timing clock 1 3 4 8 2 2 3 t irq 6 5 7 7 11 clock setup 10 9 stop mode recovery source in n
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 92 for the values in table 58, sclk tclk = crystal 2, within a standard temper- ature range of 0oc to 70oc. table 58. additional timing at standard temperature no sym parameter v cc 1 t a = 0oc to +70oc units notes d1,d0 8 mhz 12 mhz min max min max 1t p c input clock period 4.5v 250 dc 83 dc ns 2,3,4 5.5v 250 dc 83 dc ns 2,3,4 4.5v 125 dc 250 dc ns 2,3 5.5v 125 dc 250 dc ns 2,3 2t r c, t f c clock input rise & fall times 4.5v 25 15 ns 2,3 5.5v 25 15 ns 2,3 3t w c input clock width 4.5v 125 41 ns 2,3,4 5.5v 125 41 ns 2,3,4 4.5v 62 125 ns 2,3 5.5v 62 125 ns 2,3 4t w t in l timer input low width 4.5v 100 100 ns 2,3 5.5v 70 70 ns 2,3 5t w t in h timer input high width 4.5v 3t p c5t p c2,3 5.5v 3t p c5t p c2,3 6t p t in timer input period 4.5v 4t p c8t p c2,3 5.5v 4t p c8t p c2,3 7t r t in , t f t in timer input rise & fall timer 4.5v 100 100 ns 2,3 5.5v 100 100 ns 2,3 notes: 1. the v cc voltage speci?cation of 4.5v guarantees 3.3v 0.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v. 2. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 3. smr: d1 = 0. 4. the maximum frequency for the external crystal clock is 4 mhz when using low-emi oscillator mode. 5. the interrupt request via port 3 (p31Cp33). 6. the interrupt request via port 3 (p30). 7. smr: d5 = 1, and the por stop-mode delay is on. 8. for rc and lc oscillators, and for an oscillator driven by a clock driver. 9. the d1,d0 column applies to the watch-dog timer mode register tap selection. 10. 12 s is the typical delay time; only applies when smr register bit d5 is cleared to 0
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 93 8a t w il interrupt request low time 4.5v 100 100 ns 2,3,5 5.5v 70 70 ns 2,3,5 8b t w il interrupt request low time 4.5v 3t p c5t p c 2,3,6 5.5v 3t p c5t p c 2,3,6 9t w ih interrupt request input high time 4.5v 3t p c5t p c 2,3,5 5.5v 3t p c5t p c 2,3,5 10 t wsm stop-mode recovery width spec 4.5v 12 12 ns 7 5.5v 12 12 ns 7 11 t ost oscillator startup time 4.5v 5t p c5t p c7,8 5.5v 5t p c5t p c7,8 12 t wdt watch-dog timer delay timer before time-out 4.5v 7 ms 9 0,0 5.5v 3.5 ms 9 0,0 4.5v 14 ms 9 0,1 5.5v 7 ms 9 0,1 4.5v 28 ms 9 1,0 5.5v 14 ms 9 1,0 4.5v 112 ms 9 1,1 5.5v 56 ms 9 1,1 table 58. additional timing at standard temperature (continued) no sym parameter v cc 1 t a = 0oc to +70oc units notes d1,d0 8 mhz 12 mhz min max min max notes: 1. the v cc voltage speci?cation of 4.5v guarantees 3.3v 0.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v. 2. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 3. smr: d1 = 0. 4. the maximum frequency for the external crystal clock is 4 mhz when using low-emi oscillator mode. 5. the interrupt request via port 3 (p31Cp33). 6. the interrupt request via port 3 (p30). 7. smr: d5 = 1, and the por stop-mode delay is on. 8. for rc and lc oscillators, and for an oscillator driven by a clock driver. 9. the d1,d0 column applies to the watch-dog timer mode register tap selection. 10. 12 s is the typical delay time; only applies when smr register bit d5 is cleared to 0
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 94 13 t por power-on reset delay 4.5v 3 24 ms 5.5v 1.5 13 ms 14 t edelay por delay time 4.5v 35 s 10 5.5v 35 s 10 table 58. additional timing at standard temperature (continued) no sym parameter v cc 1 t a = 0oc to +70oc units notes d1,d0 8 mhz 12 mhz min max min max notes: 1. the v cc voltage speci?cation of 4.5v guarantees 3.3v 0.3v, and the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v. 2. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 3. smr: d1 = 0. 4. the maximum frequency for the external crystal clock is 4 mhz when using low-emi oscillator mode. 5. the interrupt request via port 3 (p31Cp33). 6. the interrupt request via port 3 (p30). 7. smr: d5 = 1, and the por stop-mode delay is on. 8. for rc and lc oscillators, and for an oscillator driven by a clock driver. 9. the d1,d0 column applies to the watch-dog timer mode register tap selection. 10. 12 s is the typical delay time; only applies when smr register bit d5 is cleared to 0
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 95 for the values in table 59, sclk tclk = crystal 2, within an extended tem- perature range of C40oc to 105oc. table 59. additional timing at extended temperature no sym parameter v cc 1 t a = C40oc to +105oc units notes d1,d0 8 mhz 12 mhz min max min max 1t p c input clock period 4.5v 250 dc 83 dc ns 2,3,4 5.5v 250 dc 83 dc ns 2,3,4 4.5v 125 dc 250 dc ns 2,3 5.5v 125 dc 250 dc ns 2,3 2t r c, t f c clock input rise & fall times 4.5v 25 15 ns 2,3 5.5v 25 15 ns 2,3 3t w c input clock width 4.5v 125 41 ns 2,3,4 5.5v 125 41 ns 2,3,4 4.5v 62 125 ns 2,3 5.5v 62 125 ns 2,3 4t w t in l timer input low width 4.5v 100 100 ns 2,3 5.5v 70 70 ns 2,3 5t w t in h timer input high width 4.5v 3t p c5t p c2,3 5.5v 3t p c5t p c2,3 6t p t in timer input period 4.5v 4t p c8t p c2,3 5.5v 4t p c8t p c2,3 7t r t in , t f t in timer input rise & fall timer 4.5v 100 100 ns 2,3 5.5v 100 100 ns 2,3 notes: 1. the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v. 2. the timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 3. smr: d1 = 0. 4. the maximum frequency for the external crystal clock is 4 mhz when using low-emi oscillator mode. 5. the interrupt request via port 3 (p31Cp33). 6. the interrupt request via port 3 (p30). 7. smr: d5 = 1, and the por stop-mode delay is on. 8. for rc and lc oscillators, and for an oscillator driven by a clock driver. 9. the d1,d0 column applies to the watch-dog timer mode register tap selection. 10. 12 s is the typical delay time.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 96 8a t w il interrupt request low time 4.5v 100 100 ns 2,3,5 5.5v 70 70 ns 2,3,5 8b t w il interrupt request low time 4.5v 3t p c5t p c 2,3,6 5.5v 3t p c5t p c 2,3,6 9t w ih interrupt request input high time 4.5v 3t p c5t p c 2,3,5 5.5v 2t p c5t p c 2,3,5 10 t wsm stop-mode recovery width spec 4.5v 12 12 ns 7 5.5v 12 12 ns 7 11 t ost oscillator startup time 4.5v 5t p c5t p c7,8 5.5v 5t p c5t p c7,8 12 t wdt watch-dog timer delay timer before time-out 4.5v 7 ms 9 0,0 5.5v 3.5 ms 9 0,0 4.5v 14 ms 9 0,1 5.5v 7 ms 9 0,1 4.5v 28 ms 9 1,0 5.5v 14 ms 9 1,0 4.5v 112 ms 9 1,1 5.5v 56 ms 9 1,1 13 t por power-on reset delay 4.5v 3 25 ms 5.5v 1 14 ms table 59. additional timing at extended temperature (continued) no sym parameter v cc 1 t a = C40oc to +105oc units notes d1,d0 8 mhz 12 mhz min max min max notes: 1. the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v. 2. the timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 3. smr: d1 = 0. 4. the maximum frequency for the external crystal clock is 4 mhz when using low-emi oscillator mode. 5. the interrupt request via port 3 (p31Cp33). 6. the interrupt request via port 3 (p30). 7. smr: d5 = 1, and the por stop-mode delay is on. 8. for rc and lc oscillators, and for an oscillator driven by a clock driver. 9. the d1,d0 column applies to the watch-dog timer mode register tap selection. 10. 12 s is the typical delay time.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 97 14 t edelay por delay time 4.5v 35 s 10 5.5v 35 s 10 figure 27. input handshake timing table 59. additional timing at extended temperature (continued) no sym parameter v cc 1 t a = C40oc to +105oc units notes d1,d0 8 mhz 12 mhz min max min max notes: 1. the v cc voltage speci?cation of 5.5v guarantees 5.0v 0.5v. 2. the timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 3. smr: d1 = 0. 4. the maximum frequency for the external crystal clock is 4 mhz when using low-emi oscillator mode. 5. the interrupt request via port 3 (p31Cp33). 6. the interrupt request via port 3 (p30). 7. smr: d5 = 1, and the por stop-mode delay is on. 8. for rc and lc oscillators, and for an oscillator driven by a clock driver. 9. the d1,d0 column applies to the watch-dog timer mode register tap selection. 10. 12 s is the typical delay time. data in 1 3 4 5 6 dav (input) rdy (output) next data in valid delayed rdy delayed dav data in valid 2
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 98 figure 28. output handshake timing table 60. handshake timing 1 at standard temperature no symbol parameter v cc 2 12 mhz units data direction min max 1t s di(dav) data in setup time 4.5v 0 ns input 5.5v 0 ns input 2t h di(rdy) data in hold time 4.5v 0 ns input 5.5v 0 ns input 3t w dav data available width 4.5v 155 ns input 5.5v 110 ns input 4t d davi(rdy) dav fall to rdy fall delay 4.5v 0 ns input 5.5v 0 ns input 5t d david(rdy) dav out to dav fall delay 4.5v 120 ns input 5.5v 80 ns input 6 rdy0 d (dav) rdy rise to dav fall delay 4.5v 0 ns input 5.5v 0 ns input 7 t d d0(dav) data out to dav fall delay 4.5v 42 ns output 5.5v 42 ns output 8t d dav0(rdy) dav fall to rdy fall delay 4.5v 0 ns output 5.5v 0 ns output notes: 1. the timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. the v cc voltage specification of 5.5v guarantees 5.0v 0.5v. data out dav (output) rdy (input) next data out valid delayed rdy delayed dav data out valid 7 8 9 10 11
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 99 9t d rdy0(dav) rdy fall to dav rise delay 4.5v 160 ns output 5.5v 115 ns output 10 t w rdy rdy width 4.5v 110 ns output 5.5v 80 ns output 11 t d rdy0 d (dav) rdy rise to dav fall delay 4.5v 110 ns output 5.5v 80 ns output table 61. handshake timing 1 at extended temperature no symbol parameter v cc 2 12 mhz 16 mhz units data direction min max min max 1t s di(dav) data in setup time 4.5v 0 0 ns input 5.5v 0 0 ns input 2t h di(rdy) data in hold time 4.5v 0 0 ns input 5.5v 0 0 ns input 3t w dav data available width 4.5v 155 155 ns input 5.5v 110 110 ns input 4t d davi(rdy) dav fall to rdy fall delay 4.5v 0 0 ns input 5.5v 0 0 ns input 5t d david(rdy) dav out to dav fall delay 4.5v 120 120 ns input 5.5v 80 80 ns input 6 rdy0 d (dav) rdy rise to dav fall delay 4.5v 0 0 ns input 5.5v 0 0 ns input 7 t d d0(dav) data out to dav fall delay 4.5v 42 31 ns output 5.5v 42 31 ns output notes: 1. the timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. the v cc voltage specification of 5.5v guarantees 5.0v 0.5v. table 60. handshake timing 1 at standard temperature (continued) no symbol parameter v cc 2 12 mhz units data direction min max notes: 1. the timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. the v cc voltage specification of 5.5v guarantees 5.0v 0.5v.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 100 standard test conditions the characteristics listed in following pages apply for standard test conditions as noted. all voltages are referenced to gnd. positive current ?ows into the refer- enced pin (see figure 29.) 8t d dav0(rdy) dav fall to rdy fall delay 4.5v 0 0 ns output 5.5v 0 0 ns output 9t d rdy0(dav) rdy fall to dav rise delay 4.5v 160 160 ns output 5.5v 115 115 ns output 10 t w rdy rdy width 4.5v 110 110 ns output 5.5v 80 80 ns output 11 t d rdy0 d (dav ) rdy rise to dav fall delay 4.5v 110 110 ns output 5.5v 80 80 ns output figure 29. test load diagram table 61. handshake timing 1 at extended temperature (continued) no symbol parameter v cc 2 12 mhz 16 mhz units data direction min max min max notes: 1. the timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. the v cc voltage specification of 5.5v guarantees 5.0v 0.5v. from output under test 150 pf
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary electrical characteristics 101 capacitance table 62. capacitance* parameter min max input capacitance 0 12 pf output capacitance 0 12 pf i/o capacitance 0 12 pf note: *t a = 25oc, v cc = gnd = 0v, f = 1.0 mhz, unmeasured pins to gnd.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary one-time programming 102 one-time programming table 63 brie?y describes the muze family otp option bit selection at each bits default value before programming. eprom protect. selecting the disable eprom protect option, bit 0, allows the software program that is in the program memory to be read using zilogs internal factory test mode. selecting the enable eprom protect option negates the possibility of reading the code out of the part using a tester, program- mer, or any other standard method. the eprom protect option bit only affects the parts ability to read from an external source and does not affect the operation of the part in an application. ram protect. selecting the disable ram protect option, bit 1, does not affect the ram memory. ram memory operates as de?ned in this product speci- ?cation for all address locations. selecting the enable ram protect option, allows protection (under software control) of a portion of the rams address space from being read or written. table 63. option bit description* bit option unprogrammed default value 0 eprom protect disabled 1 ram protect disabled 2 autolatches enabled 3 p0 pull-ups disabled 4 p1 pull-ups disabled 5 p2 pull-ups disabled 6 rc oscillator disabled 7 32-khz oscillator disabled 8 permanent wdt disabled 9 vbo enabled 10 reserved must not be changed 11 reserved must not be changed 12 reserved must not be changed 13 reserved must not be changed 14 reserved must not be changed 15 reserved must not be changed note: *option bits are 0 when unprogrammed and are 1 when programmed. if bits are not to be programmed, use 0.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary one-time programming 103 autolatch mode. selecting the disable autolatches option, bit 2, dis- ables the autolatches on the port pins. these pins ?oat, rather than are pulled, to a valid cmos level when they are inputs and not connected to an external signal. selecting the enable autolatches option enables the autolatches on the port pins and pulls the pins to a valid cmos level when they are not connected to an external signal. port 0 pull-ups. selecting disable pull-ups option, bit 3, disables the input pull-up circuitry on all port 0 pins. selecting enable pull-ups enables the input pull-up circuitry on all port 0 pins. this option bit does not affect any of the other port pins on the part. port 1 pull-ups. selecting disable pull-ups option, bit 4, disables the input pull-up circuitry on all port 1 pins. selecting enable pull-ups enables the input pull-up circuitry on all port 1 pins. this option bit does not affect any of the other port pins on the part. port 2 pull-ups. selecting disable pull-ups option, bit 5, disables the input pull-up circuitry on all port 2 pins. selecting enable pull-ups enables the input pull-up circuitry on all port 2 pins. this option bit does not affect any of the other port pins on the part. system clock source. selecting the rc oscillator enable option, bit 6, con- ?gures the oscillator circuit on the microcontroller to work with an external rc cir- cuit. selecting the crystal/other clock source option con?gures the oscillator circuit to work with an external crystal, ceramic resonator, or lc oscilla- tor. oscillator operational mode. selecting the normal high frequency oper- ation enabled option, bit 7, enables the part to operate using a standard crys- tal or resonator, but it does not operate using a 32-khz crystal. selecting the 32- khz operation enabled option enables the microcontroller to work with a 32-khz crystal and an external feedback resistorthese 2 items must be supplied between the x in and x out pins. (if rc oscillator enabled is selected in the system clock source option, this option defaults to the normal high frequency operation enabled bit.) wdt mode. selecting the wdt enabled by software only option, bit 8, operates the watch-dog timer (wdt) when turned on under software control. selecting the wdt enabled automatically after reset option starts the wdt automatically at reset.there is no way to disable or stop this mode, making it necessary in the code to periodically clear the wdt to prevent it from resetting the microcontroller. if the wdt enabled automatically after reset option and the wdt driven by system clock option (if offered) are selected, the wdt never operates in stop mode, and cannot be enabled, by any means, to operate in stop mode.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary one-time programming 104 vbo. selecting the vbo option, bit 9, enables low-voltage protection circuitry. the device resets if v cc goes below v lv when vbo is selected. if it is disabled, the device does not reset if v cc falls below v lv . see low-voltage protection for more details. the remainder of the otp options, bits 10C15, are reserved by zilog and must not be changed from their default values.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 105 universal asynchronous receiver/transmitter asci key features key features of the uart asynchronous serial communications interface (asci) include: ? full-duplex operation ? programmable data format ? 7 or 8 data bits with optional ninth bit for multiprocessor communication ? p30 and p37 are used as general-purpose i/o as long as the asci channels are disabled ? one or two stop bits ? odd, even or no parity ? programmable interrupt conditions ? four level data/status fifos for the receiver ? receive parity, framing and overrun error detection ? break detection and generation transmit data register. data written to the asci transmit data register (tdr) is transferred to the transmit shift register (tsr) as soon as the tsr is empty. data is written while the tsr shifts the previous byte of data, thereby providing a double buffer for the transmit data. the tdr is read- and write-accessible. reading from the tdr does not affect the asci data transmit operation currently in progress. transmit shift register. when the transmit shift register (tsr) receives data from the asci transmit data register, the data shifts to the tx (p37) pin. when transmission is completed, the next byte, if available, is automatically loaded from the tdr into the tsr. the next transmission then starts. if no data is available for transmission, the tsr idles at a continuous high level. this register is not pro- gram-accessible. receive shift register. when the receive enable (re) bit is set in the cntla register, the rx (p30) pin is monitored for a low. one-half bit-time after a low is sensed at rx, the asci samples rx again. if rx goes back to high, the asci ignores the previous low and resumes looking for a new low. however, if rx is still low, it considers rx a start bit and proceeds to clock in the data based upon the selected baud rate. the number of data bits, parity, multiprocessor and stop bits are selected by the mod2, mod1, mod0 and multiprocessor mode (mp) bits in the cntla and cntlb registers.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 106 after the data is received, the appropriate mp, parity and stop bits are checked. data and any errors are clocked into the receive data and status fifo during the stop bit if there is an empty position available. interrupts and receive data reg- ister full flag also goes active during this time. if there is no space in the fifo at the time that the rsr attempts to transfer the received data into it, an overrun error occurs. receive data fifo. when a complete incoming data byte is assembled in the rsr, it is automatically transferred to the 4-byte fifo, which serves to reduce the incidence of overrun errors. the top (oldest) character in the fifo (if any) is read via the receive data register (rdr). the next incoming data byte can shift into the rsr while the fifo is full, thus pro- viding an additional level of buffering. however, an overrun occurs if the receive fifo is still full when the receiver completes assembly of that character and is ready to transfer it to the fifo. if this situation occurs, the overrun error bit is set in the previous byte of the fifo stack. figure 30. receive data register fifo data byte 1 data byte 2 data byte 3 data byte 4 rsr flags flags flags flags
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 107 the latest data byte is not transferred from the shift register to the fifo in this case, and is lost. when an overrun occurs, the receiver does not place any further data in the fifo until the most recent good byte received arrives at the top of the fifo and sets the overrun latch, and software then clears the overrun latch by a write of 0 to the efr bit. figure 31. fifo overrun example figure 32. clear fifo overrun example good data byte 1 good data byte 2 good data byte 3 good data byte 4 overrun data byte (lost data) flags flags flags flags sets flag good data byte 4 empty empty empty ignored data bytes overrun flag empty empty empty
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 108 assembly of bytes continues in the shift register, but this data is ignored until the byte with the overrun error reaches the top of the fifo and the status is cleared. when a break occurs (de?ned as a framing error with the data equal to all zeros), the all-zero byte, with its associated error bits, are transferred to the fifo if it is not full. as a result, the break detect bit (bit 1) is set in the asext register. if the fifo is full, an overrun is generated, but the break, framing error and data are not transferred to the fifo. any time a break is detected, the receiver does not receive any more data until the rx pin returns to a high state. if the channel is set in multiprocessor mode and the mpe bit (bit 7) of the cntla register is set to 1, then break, errors and data are ignored unless the mp bit in the received character is 1. the two conditions listed above could cause the missing of a break condition if the fifo is full and the break occurs or if the mp bit in the transmission is not a one with the conditions speci?ed above. asci status fifo/registers this fifo contains parity error, framing error, rx overrun, and break status bits associated with each character in the receive data fifo. the status of the oldest character (if any) is read from the asci status reg- ister, which also provides several other, non-fifoed status conditions. the outputs of the error fifo set the inputs of the software-accessible error latches in the status register. writing a 0 to the efr bit (bit 3) in cntla is the only way to clear these latches. in other words, when an error bit reaches the top of the fifo, it sets an error latch. if the fifo contains more data and the software reads the next byte out of the fifo, the error latch remains set until the software writes a 0 to the efr bit. the error bits are cumulative, so if additional errors are in the fifo they set any unset error latches as they reach the top. baud rate generator (brg) the baud rate generator features two modes. the ?rst provides a dual set of ?xed clock divide ratios as de?ned in cntlb. in the second mode, the brg is con?gured as a sixteen-bit down counter that divides the pro- cessor clock by the value in a software accessible, sixteen-bit, time-constant reg- ister. as a result, virtually any frequency is created by appropriately selecting the main processor clock frequency. the brg can also be disabled in favor of the sclk. the receiver and transmitter subsequently divide the output of the baud rate generator (or the signal from the clk pin) by 1, 16 or 64 under the control of the dr bit (bit 3) in the cntlb register and the x1 bit in the asci extension control register (asext). reset during reset, the asci is forced to the following conditions: ? fifo empty ? all error bits cleared (including those in the fifo) ? receive enable cleared (cntla bit 6 = 0) ? transmit enable cleared (cntla bit 5 = 0)
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 109 asci interrupts the asci channel generates one interrupt, irq3, from two sources of interrupts: a receiver and a transmitter. in addition, there are several conditions that may cause these interrupts to trigger. figure 64 illustrates the different conditions for each interrupt source enabled under program control. figure 33. asci interface diagram internal address/data bus asci transmit data register tdr (bank: ah, addr: 01h) asci status fifo/register stat (bank: ah, addr: 08h) asci transmit shift register tsr* asci receive data fifo rdr (bank: ah, addr: 02h) asci receive shift register rsr* asci control register a cntla (bank: ah, addr: 03h) asci control register b cntlb (bank: ah, addr: 04h) asci extension control reg. asext (bank: ah, addr: 05h) asci time constant high astch (bank: ah, addr: 07h) asci time constant low astcl (bank: ah, add: 06h) baud rate generator sclk (p37) tx (p30) rx asci control irq3 interrupt request note: *not programmed.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 110 asci transmit data register data written to the asci transmit data register (tdr) is transferred to the trans- mit shift register (tsr) as soon as the tsr is empty. the tsr is not software- accessible. the asci transmitter is double-buffered so data can be written to the tdr while the tsr is shifting out the previous byte. data can be written into and read out of the tdr. when the tdr is read, the data transmit operation is not affected. read/write and reset states for bits d7Cd0 of the tdr are listed in table 65. asci receive data register when a complete incoming data byte is assembled in the receive shift register (rsr), it is automatically transferred to the highest available location in the table 64. asci interrupt conditions and sources table 65. transmit data registertdr 01h/r1 bank ah: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxx x xxx note: r = read, w = write, x = indeterminate. bit/ field bit position r/w state description d7Cd0 tdr r/w x transmit data register transmitter interrupt sources receiver interrupt sources asci interrupt (irq3) fifo full overrun error framing error parity error start bit buffer empty
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 111 receive data fifo. the receive data register (rdr) is the highest location in the receive data fifo. the receive data register not empty bit (rdrnebit 7) in the stat register is set when one or more bytes is available from the fifo. the fifo status for the character in the rdr is available in the stat register via bits 6, 5 and 4. stat should be read before reading the rdr. the data in both fifo locations is popped when the character is read from the rdr. read/write and reset states for bits d7Cd0 of the rdr are listed in table 66. asci control register a asci control register a, cntla, controls data transmit, receive, and clocking functions. read/write and reset states for bits d7Cd0 are listed in table 67. table 66. receive data registerrdr 02h/r2 bank ah: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset xxxx x xxx note: r = read, w = write, x = indeterminate. bit/ field bit position r/w state description d7Cd0 rdr r/w x receive data register table 67. control register acntla 03h/r3 bank ah: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0001 0 000 note: r = read, w = write, x = indeterminate. bit/field bit position r/w state description d7 mpe r/w 0 multiprocessor enable 0: receive all bytes 1: filter bytes with mpb = 0 d6 re r/w 0 receiver enable 0: asci receiver disabled (p30 = input) 1: asci receiver enabled (p30 = rx)
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 112 multiprocessor enable. the asci features a multiprocessor communication mode that utilizes an extra data bit for selective communication when a number of pro- cessors share a common serial bus. multiprocessor data format is selected when the mp in the corresponding register is set to 1. if multiprocessor mode is not selected (mp bit in cntlb = 0), multiprocessor enable (mpe, bit 7) exhibits no effect. if multiprocessor mode is selected (mpe bit in cntlb = 1), mpe enables or disables the wake-up feature as follows. if mpe is set to 1, only received bytes in which the multiprocessor bit (mpb) = 1 are treated as valid data characters and loaded into the receiver fifo with corresponding error ?ags in the status fifo. bytes with mpb = 0 are ignored by the asci. if mpe is reset to 0, all bytes are received by the asci, regardless of the state of the mpb data bit. receiver enable. when receiver enable (re, bit 6) is set to 1, the asci receiver is enabled. when re is reset to 0, the receiver is disabled and any receive opera- tion in progress is aborted. however, the previous contents of the receiver data and status fifo are not affected. transmitter enable. when transmitter enable (te, bit 5) is set to 1, the asci transmitter is enabled. when te is reset to 0, the transmitter is disabled and any transmit operation in progress is aborted. however, the previous contents of the d5 te r/w 0 transmitter enable 0: asci transmitter disabled (p37 = output) 1: asci transmitter enabled (p37 = tx) d4 reserved r/w 1 reserved d3 mpbr r0 multiprocessor bit received efr w0 error flag reset 0: clear error latches 1: no effect d2Cd0 mod2C0 r0 mod2number of data bits 0: 7 data bits 1: 8 data bits mod1parity enabled 0: no parity 1: with parity mod0number of stop bits 0: 1 stop bit 1: 2 stop bits bit/field bit position r/w state description
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 113 transmitter data register and the tdre ?ag (bit 1 of the stat register) are not affected. bit 4 is reserved. multiprocessor bit receive. when multiprocessor mode is enabled (mp in cntlb = 1), this read-only bit, when read, contains the value of the mpb bit for the data byte currently available at the receive data register (the top of the receiver fifo). the multiprocessor bit receive bit, mpbr, is bit 3. error flag reset. when the write-only error flag reset (efr), bit 3, is written to 0, the error ?ags (ovrn, fe; pe in stat and brk in asext) are cleared to 0. this command self-resets, and as a result, writing efr to a 1 is not required. asci data format mode. bits 2C0 program the asci data format, as indicated in table 68. if mod1 = 1, parity is checked on received data and a parity bit is appended to the data bits in the transmitted data. parity even/odd (peo) in cntlb selects even or odd parity. the asci serial data format is illustrated in figure 34. asci control register b control register b, cntlb, controls multiprocessor, parity, and clock sourcing functions. read/write and reset states for bits d7Cd0 are listed in table 69. table 68. asci data format mode control bits bit name function bit = 0 bit = 1 2 mod2 number of data bits 78 1 mod1 parity enabled no parity with parity 0 mod0 number of stop bits 12 figure 34. asci serial data format 7 or 8 bits data field parity bit 1 or 2 stop bit(s) start bit
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 114 table 69. control register bcntlb 04h/r4 bank ah: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0000 0 111 note: r = read, w = write, x = indeterminate. bit/ field bit position r/w state description d7 mpbt r/w 0 multiprocessor bit transmitter 0: transmit 0 in mpb 1: transmit 1 in mpb d6 mp r/w 0 multiprocessor mode 0: multiprocessor mode disabled 1: multiprocessor mode enabled (no parity) d5 pr w0 prescale 0: brg 10 1: brg 30 d4 peo r/w 0 parity even/odd 0: even parity 1: odd parity d3 dr r/w 0 divide ratio 0: divide by 16 1: divide by 64 d2 ss2 r1 clock source and speed bits ss2 0: 1, 2, 4, 8 1: 16, 32, 64, reserved d1 ss1 r1 clock source and speed bits ss1 0: 1, 2, 16, 32 1: 4, 8, 64, reserved d0 ss0 r1 clock source and speed bits ss0 0: 1, 4, 16, 64 1: 2, 8, 32, reserved
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 115 multiprocessor bit transmit. when multiprocessor format is selected (mp bit = 1), multiprocessor bit transmit (mpbt, bit 7) is used to specify the mpb data bit for transmission. if mpbt = 1, then a 1 is transmitted in the mpb bit position. if mpbt = 0, a 0 is transmitted. multiprocessor mode. when multiprocessor mode is set to 1, the serial data format is con?gured for multiprocessor mode (mp, bit 6), adding a bit position whose value is speci?ed in mpbt immediately after the speci?ed number of data bits and preceding the speci?ed number of stop bits. the multiprocessor format does not provide parity. the serial data format while in mp mode is illustrated in figure 35. if mp = 0, the data format is based on mod2C0 in cntla and may include parity. brg prescaler. the prescale bit speci?es the baud rate generator (brg, bit 5) prescale factor when using the ss2C0 bits to de?ne the asci baud rate (brg mode = 0). writing a 0 to this bit sets the brg prescaler to divide by 10. setting this bit to a 1 sets the brg prescaler to divide by 30. see the baud rate gener a- tion summar y for more information on setting the asci baud rate. parity even/odd. parity even/odd (peo, bit 4) controls the parity bit transmitted on the serial output and the parity check on the serial input. if peo is cleared to 0, even parity is transmitted and checked. if peo is set to 1, odd parity is transmitted and checked. divide ratio. the divide ratio bit (dr, bit 3) speci?es the divider used to obtain the baud rate from the data sampling clock when using the ss2C0 bits to de?ne the asci baud rate (brg mode = 0). if dr is 0, then divide-by-16 is used. if dr is set to 1, then divide-by-64 is used. see the baud rate gener ation summar y for more information on setting the asci baud rate. figure 35. multiprocessor mode serial data format note: 7 or 8 bits data field mpb 1 or 2 stop bit(s) start bit
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 116 clock source and speed select. when the brg mode bit (bit 3) in the asext reg- ister is set to 0, these 3 bits, along with dr and pr in this register de?ne the asci baud rate. bits 2, 1 and 0 specify a power-of-two divider of the sclk as de?ned in table 70. these bits should never be set to all 1s or erratic results may occur. see the baud rate gener ation summar y for more information on setting the asci baud rate. asci extension control register following are the bit functions for the asci extension control register (asext). dr sampling clock 0 divide by 16 1 divide by 64 table 70. clock source and speed bits ss2 ss1 ss0 divider (div) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 reserved table 71. extension control registerasext 05h/r5 bank ah: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r r/w r/w r/w r/w r/w r r/w reset p30 0 0 0 0 0 0 0 note: r = read, w = write, x = indeterminate. bit/ field bit position r/w state description d7 rx r p30 rx data state d6 reserved r/w 0 reserved d5 reserved r/w 0 reserved
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 117 rx state. this bit provides the real-time state of the channels receive data input pin (rx, bit 7), which is p30. reserved bits 6, 5, and 4. when read, bits 6 and 5 re?ect the default value 0. when written, these bits are ignored. bit 4 must be set to 0 or erratic results may occur. brg mode. when the baud rate generator (brg, bit 3) bit is set to 1, the ascis baud rate is set by the 16-bit programmable divider programmed in asci time constant high (asth) and asci time constant low (astl). if this bit is set to 0, the baud rate is de?ned by the pr bit, the dr bit, and the ss2C0 bits in the cntlb register. in either case, the source for the baud rate generator is the sclk. see the baud rate gener ation summar y for more information on setting the asci baud rate. rx interrupt on start. if software sets rx (bit 2) to 1, a receive interrupt is requested (in a combinatorial fashion) when a start bit is detected on rx. such a receive interrupt is always followed by setting rdrne (bit 7) in the middle of the stop bit. upon receiving the interrupt service request, the rx interrupt on start (ris) bit must be set to 0, then immediately set to 1 to continue operation with a start bit interrupt. one function of this feature is to wake the part from halt mode when a character arrives, so that the asci receives clocking to process the char- acter. another function is to ensure that the associated interrupt service routine is activated in time to sense the setting of rdrne in the status register, and to start a timer for baud rate measurement at that time. break detect. this read-only status bit (bd, bit 1)is set to 1 when a break is detected. a break is de?ned as a framing error with the data bits all equal to 0. the all-zero byte with its associated error bits are transferred to the fifo if it is not full. if the fifo is full, an overrun is generated, but the break, framing error and data are not transferred to the fifo. any time a break is detected, the receiver does not receive any more data until the rx pin returns to a high state. when set, d4 reserved r/w 0 reserved (must be 0) d3 brg r/w 0 baud rate generator mode 0: use ss selection 1: use asth or astl value d2 ris r/w 0 rx interrupt on start bit 0: no irq on start bit 1: irq3 on start bit d1 bd r0 break detect 0: valid data byte 1: break detected d0 sb r/w 0 send break 0: normal operation 1: send break
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 118 this bit remains set until it is cleared by writing a 0 to the efr bit in the cntla register. send break. setting the sb bit (bit 0) to a 1 forces the channels transmitter data output pin, tx, to a low for as long as it remains set. before starting the break, any character(s) in the tsr and in the tdr are transmitted completely. if a char- acter is loaded into the tdr while a break is being generated, that character is held until the break is terminated and then transmitted. asci time constant registers the astl and asth registers are only used when the brg mode bit in the asext register is set to 1. these two 8-bit registers form a 16-bit counter with a ?ip-?op logic circuit (divide-by-2) on the output so that the ?nal brg output is symmetrical. the values written to these registers determine the time constant from which the baud rate is generated. read/write and reset states for bits d7Cd0 of the astl and asth registers are listed in tables 72 and 73, respectively. table 72. time constant register lowastl 06h/r6 bank ah: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1111 1 111 note: r = read, w = write, x = indeterminate. bit/ field bit position r/w state description d7Cd0 astl r/w 1 asci time constant low table 73. time constant register highasth 07h/r7 bank ah: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 1111 1 111 note: r = read, w = write, x = indeterminate. bit/ field bit position r/w state description d7Cd0 asth r/w 1 asci time constant high
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 119 asci status register the asci status register, s tat, controls status functions. read/write and reset states for bits d7Cd0 are listed in table 74. receive data register not empty. rdrne (rdrne, bit 7)is set to 1 when the receiver transfers a character from the rsr into an empty rx fifo. if a framing or parity error occurs, rdrne is still set and the receive data (which generated the error) is still loaded into the fifo. table 74. status registerstat 08h/r8 bank ah: read/write bit d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r/wr/wrr/w reset 0000 0 010 note: r = read, w = write, x = indeterminate. bit/ field bit position r/w state description d7 rdrne r0 receive data register not empty 0: receive fifo empty 1: receive fifo contains 1 or more bytes d6 oe r0 overrun error 0: receive ok 1: next byte is a fifo overrun d5 pe r0 parity error 0: parity ok 1: parity error d4 fe r0 framing error 0: receive ok 1: framing error d3 rie r/w 0 receive interrupt enable 0: no irq on receive 1: irq3 on rdrne or start bit d2 reserved r/w 0 reserved d1 tdre r1 transmit data register empty 0: transmitter working 1: transmit buffer empty d0 tie r/w 0 transmit interrupt enable 0: no irq on transmit 1: irq3 on tdre note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 120 when there is more than one byte in the fifo and software reads a byte, rdrne is not cleared to 0. the bit is cleared when the last byte is read from the fifo. overrun error. an overrun error (oe, bit 6) occurs if the receive fifo is still full when the receiver completes assembly of a character and is ready to transfer it to the fifo. if this situation occurs, the overrun error bit associated with the previous byte in the fifo is set. in this case, the latest data byte is not transferred from the shift register to the fifo and is lost. when an overrun occurs, the receiver does not place any further data in the fifo until the most recent good byte received (the byte with the associated overrun error bit set) moves to the top of the fifo and sets the overrun latch, and soft- ware then clears the overrun latch. assembly of bytes continues in the shift regis- ter, but this data is ignored until the byte with the overrun error reaches the top of the fifo and the status is cleared. when set, the bit remains set until it is cleared by writing a 0 to the efr bit in the cntla register. the bit is also cleared during power-on reset. parity error. a parity error (pe, bit 5) is detected when parity generation and checking is enabled by the mod1 bit (bit 1) in the cntla register and a character is assembled in which the parity does not match that speci?ed by the peo bit (bit 4) in cntlb. pe is fifoed and the error bit is not actually set until the associated data becomes available for reading in the rdr . when set, the bit remains set until it is cleared by writing a 0 to the efr bit (bit 3) in the cntla register. the bit is cleared at power-on reset. framing error. a framing error (fe, bit 4) is detected when the stop bit of a char- acter is sampled as a 0 (space). like pe, fe is fifoed and the error bit is not actually set until the associated data becomes available for reading in the rdr. when set, the bit remains set until it is cleared by writing a 0 to the efr bit (bit 3) in the cntla register. the bit is cleared at power-on reset. receive interrupt enable. rie, bit 3, must be set to 1 to enable asci receive inter- rupt requests. the z8 edge-triggered interrupt (irq3) is generated when rdrne (bit 7 of the stat register) is transitioned from 0 to 1. irq3 is also generated if a start bit is detected; the rie bit is set to 1, and bit 2 of the asext register is set to 1. reserved bit 2. when read, bit 2 re?ects the default value 0. when written, bit 2 is ignored. transmit data register empty. tdre = 1 indicates that the transmit data register (tdr) is empty and that the next data byte to be transmitted can be written into the tdr. tdre, bit 1, is cleared to 0 after the byte is written to tdr, until the asci transfers the byte from the tdr to the transmit shift register (tsr), and then tdre is again set to 1. tdre is set to 1 at power-on reset. note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 121 transmit interrupt enable. tie, bit 0, should be set to 1 to enable asci transmit interrupt requests. an interrupt (irq3) is generated when tdre (bit 1 of the stat register) transitions from 0 to 1. tie is cleared to 0 at power-on reset. if both tie and rie are set to 1, a receive interrupt is not generated on the incoming (rdr) data. to generate a receive interrupt: 1. the user must set only rie to 1. 2. if both tie and rie have been previously set to 1, zilog recommends that the efr flag also be cleared to 0. if the efr flag is not cleared to 0, the receive interrupt may not occur. clear the efr flag bit with the following instruction: push rp ;save the register pointer srp #%1a ;switch to the asci control register ;bank loop1:ld temp,rdr ;clean up the rdr register tm stat,#10000000b ;make sure no data exists ;in the rdr fifo jr nz,loop1 and cntla,#11110111b :clear efr pop rp ;restore the register pointer baud rate generation summary the application can select between one of two baud rate generators for the asci. if the brg mode bit in the asext register is set to 0, the ss2,1,0 bits, the dr bit, and the pr bit in cntlb are used to select the baud rate. if the brg mode bit is set to 1, the astl and asth registers are used to select the baud rate. the following formulas are used to calculate the baud rate from the two baud rate generators: if brg mode = 0: where: 1. sclk is the system clock. 2. ps = 1 or 0 and is bit 5 of cntlb. 3. div = 1, 2, 4, 8, 16, 32 or 64 as re?ected by ss2C0 in cntlb. 4. divide ratio = 16 or 64, as de?ned by dr (bit 3) in cntlb. if brg mode = 1: baud rate = sclk (10 + 20 x ps) x div x divide ratio note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 122 or where: 1. sclk is the system clock. 2. tc is the 16-bit value programmed in astl and asth. a minimum tc value of 0 is valid. 3. divide ratio = 16 or 64, as de?ned by dr in cntlb. 4. baud rate is the desired baud rate. 5. a maximum baud rate of 115kbps can be obtained by using a 16-mhz crystal, when tc = 0 and the divide ratio = 16. baud rate = sclk (2 x (tc + 2) x divide ratio tc = sclk C 2 2 x baud rate x divide ratio
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 123 table 75. baud rate listbrg mode = 0 prescaler sampling rate baud rate general divide ratio example baud rate (bps) ps divide ratio dr rate ss2 ss1 ss0 divide ratio sclk = 6.144 mhz sclk = 4.608 mhz sclk = 3.072 mhz 0 sclk 10 0 16 0 0 0 1 sclk 160 38400 19200 001 2 sclk 320 19200 9600 010 4 sclk 640 9600 4800 011 8 sclk 1280 4800 2400 10016 sclk 2560 2400 1200 10132 sclk 5120 1200 600 11064 sclk 10240 600 300 164000 1 sclk 640 9600 4800 001 2 sclk 1280 4800 2400 010 4 sclk 2560 2400 1200 011 8 sclk 5120 1200 600 10016 sclk 10240 600 300 10132 sclk 20480 300 150 11064 sclk 40960 150 75
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary uni versal asynchronous receiver/transmitter 124 1 sclk 30 0 16 0 0 0 1 sclk 480 4800 001 2 sclk 960 2400 010 4 sclk 1920 1200 011 8 sclk 3840 600 10016 sclk 7680 300 10132 sclk 15360 150 11064 sclk 30720 75 164000 1 sclk 1920 2400 001 2 sclk 3840 1200 010 4 sclk 7680 600 011 8 sclk 15360 300 10016 sclk 30720 150 10132 sclk 61440 75 11064 sclk 122880 37.5 table 75. baud rate listbrg mode = 0 (continued) prescaler sampling rate baud rate general divide ratio example baud rate (bps) ps divide ratio dr rate ss2 ss1 ss0 divide ratio sclk = 6.144 mhz sclk = 4.608 mhz sclk = 3.072 mhz
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary i n-circuit serial programming 125 in-circuit serial programming in-circuit serial programming block diagram figure 36 shows the basic functionality of the in-circuit serial programming inter- face (icsp). the icsp interface receives and transmits data via the sdio line in conjunction with an icsp clock on the sck line. please refer to the muze pro- g r amming speci? cation for more details. the icsp interface is a ?ve-wire connection. the connections for the muze are: v cc . power supply. sdio. serial data input/output (sdio)data input and output pin, open-drain. sck. serial icsp clock (sck)data input and output clock. icsp_reset . active low (icsp) reset. icsp_reset is an internal serial pro- gramming reset, not a complete z8 reset, as is the case with por. gnd. ground. the recommended circuit is illustrated in figure 37. figure 36. icsp block diagram icsp sdio sck eprom otp options
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary i n-circuit serial programming 126 the diode shown in figure 37 is an optional protection diode. icsp provides limited supply current. the following operations are speci?c to programming in icsp mode: ? serial operationsunlock ? serial programming option bitsword mode ? serial programming option bitsbyte mode ? serial operationsreading ? data verify ? device-speci?c options for a complete description of these operations, please refer to the muze pro- g r amming speci? cation . figure 37. icsp connectivity 1 k ? sdio gnd sck gnd gnd gnd v /icsp_reset v cc v cc v cc sck sdio v /icsp_reset z8 icsp cable header on user pcb pp pp optional protection diode. icsp provides limited supply current. icsp cable note:
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary packaging 127 packaging figure 38 illustrates the 20-pin dip package for the z86e122, z86e123, z86e124, z86e125, and z86e126 microcontroller devices. figure 38. 20-pin dip package diagram
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary packaging 128 figure 39 illustrates the 20-pin soic package for the z86e122, z86e123, z86e124, z86e125, and z86e126 microcontroller devices. figure 39. 20-pin soic package diagram
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary packaging 129 figure 40 illustrates the 28-pin dip package for the z86e132, z86e133, z86e134, z86e135, and z86e136 microcontroller devices. figure 40. 28-pin dip package diagram
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary packaging 130 figure 41 illustrates the 28-pin soic package for the z86e132, z86e133, z86e134, z86e135, and z86e136 microcontroller devices. figure 41. 28-pin soic package diagram
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary packaging 131 figure 42 illustrates the 40-pin dip package for the z86e142, z86e143, z86e144, z86e145, and z86e146 microcontroller devices. figure 42. 40-pin dip package diagram
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary packaging 132 figure 43 illustrates the 44-pin pqfp package for the z86e142, z86e143, z86e144, z86e145, and z86e146 microcontroller devices. figure 43. 44-pin pqfp package diagram
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary ordering information 133 ordering information for fast results, contact your local zilog sale of?ce for assistance in ordering the part(s) desired. table 76. ordering information size pin count package order number* 64 kb 28 dip z86e136pz016sc soic z86e136sz016sc 40 dip z86e146pz016sc 44 pqfp z86e146fz016sc 32 kb 28 dip z86e135pz016sc soic z86e135sz016sc 40 dip z86e145pz016sc 44 pqfp z86e145fz016sc 16 kb 28 dip z86e134pz016sc soic z86e134sz016sc 40 dip z86e144pz016sc 44 pqfp z86e144fz016sc 8 kb 28 dip z86e133pz016sc soic z86e133sz016sc 40 dip z86e143fz016sc 44 pqfp z86e143sz016sc 4 kb 28 dip z86e132pz016sc soic z86e132sz016sc 40 dip z86e142pz016sc 44 pqfp z86e142fz016sc note: *the standard temperature range is 0oc to 70oc. for parts that operate in the extended temperature range of C40oc to 105oc, substitute the letter e for the letter s. for example, the order number for a 28-pin dip operating at 64 kb in the extended temperature range is z86e136pz016ec.
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary ordering information 134 part number description zilog part numbers consist of a number of components. for example, part num- ber z86e136pz016sc is a 16-mhz 28-pin dip that operates in the C0oc to +70oc temperature range, with plastic standard flow. the z86e136pz016sc part num- ber corresponds to the code segments indicated in the following table. for fast results, contact your local zilog sales of?ce for assistance in ordering the part required. precharacterization product the product represented by this document is newly introduced and zilog has not completed the full characterization of the product. the document states what zilog knows about this product at this time, but additional features or non-con- formance with some aspects of the document may be found, either by zilog or its customers in the course of further application and characterization work. in addition, zilog cautions that delivery may be uncertain at times, due to start-up yield issues. zilog, inc. 910 east hamilton avenue, suite 110 campbell, ca 95008 telephone (408) 558-8500 fax 408 558-8300 internet: www .zilog.com z zilog prefix 86 z8 product e otp product 136 product number pz package 016 speed (mhz) s temperature c environmental flow
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary document information 135 document information document number description the document control number that appears in the footer of each page of this document contains unique identifying attributes, as indicated in the following table: change log ps product specification 0040 unique document number 05 revision number 1100 month and year published rev date purpose by 01 02/00 original issue k. johnston, r. beebe 02 03/00 corrections k. johnston, r. beebe 03 03/00 corrections k. johnston, r. beebe 04 06/00 corrections k. johnston, r. beebe 05 11/00 additions and corrections k. johnston, r. beebe
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary customer feedback form 136 customer feedback form muze product specification if you experience any problems while operating this product, or if you note any inaccura- cies while reading this product speci?cation, please copy and complete this form, then mail or fax it to zilog (see return information , below). we also welcome your sugges- tions! customer information product information return information zilog system test/customer support 910 e. hamilton avenue, suite 110, ms 4C3 campbell, ca 95008 fax: (408) 558-8536 email: tools@zilog.com problem description or suggestion provide a complete description of the problem or your suggestion. if you are reporting a speci?c problem, include all steps leading up to the occurrence of the problem. attach additional pages as necessary. _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ name country company phone address fax city/state/zip e-mail serial # or board fab #/rev. # software version document number host computer description/type
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary i ndex 137 index a absolute maximum ratings . . . . . . . . . . . .75 ac electrical characteristics . . . . . . . . . . . .86 additional timing . . . . . . . . . . . . . . . . . . . .91 address output . . . . . . . . . . . . . . . . . . . . . .20 address strobe . . . . . . . . . . . . . . . .12, 16, 20 ambient temperature . . . . . . . . . . . . . . . . .75 an1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 an2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 analog mode . . . . . . . . . . . . . . . . . . . . . .25 architectural overview . . . . . . . . . . . . . . . . .1 as . . . . . . . .12, 16, 20, 22, 28, 41, 56, 87C90 asci control register a . . . . . . . . . . .25, 112 asci control register b . . . . . . . . . . . . . .115 asci data format mode . . . . . . . . . . . . . .113 control bits . . . . . . . . . . . . . . . . . . . . .113 asci extension control register . . . .65, 108 asci status fifo/registers . . . . . . . . . . .108 asci time constant high register . . .66C67 asci time constant low register . . . . . . .66 asext . . . . . . . . . . . . . . . . . . . .61, 113, 116 asext register . . . . .108, 116, 118, 120C121 asth . . . . . . . . . . . . . . . . . .61, 65, 117, 121 astl . . . . . . . . . . . . . . . . . . .61, 65, 117, 121 astl register bit functions . . . . . . . .66, 118 autolatch . . . . . . . . . . . . . . . . . .24, 27, 76, 81 high current . . . . . . . . . . . . . . . . . .80, 85 low current . . . . . . . . . . . . . . . . . .79, 84 autolatch disable option . . . . . . . . . .27 autolatch mode . . . . . . . . . . . . . . . . .103 b baud rate generation . . . . . . . . . . .108, 121 break detect . . . . . . . . . . . . . . . . . . .105, 117 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 brg mode . . . . . . . . . . . .115, 117C118, 121 brg prescaler . . . . . . . . . . . . . . . . . . . . .115 byte-programmed input buffers . . . . . . . . . .22 c capacitance . . . . . . . . . . . . . . . . . . . . . . . 101 carry flag . . . . . . . . . . . . . . . . . . . . . . . . . 59 ceramic resonator . . . . . . . . . . 3, 20, 38, 103 change log . . . . . . . . . . . . . . . . . . . . . . . 135 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 clock input . . . . . . . . . . . . . . . . . . . . . . 92, 95 high voltage . . . . . . . . . . . . . . . . . 76, 81 low voltage . . . . . . . . . . . . . . . . . . 76, 81 clock source . . . . . . . . . . . . . . . . . . . . . . 116 for wdt . . . . . . . . . . . . . . . . . . . . . . . . 47 cmos- compatible . . . . . . . . . . . . 20, 22, 23 cmos level . . . . . . . . . . . . . . . . . . . . 27, 103 cntla . . . . . . . . . . 25, 61, 63, 105, 111, 115 register . . . . . . . . . . . . . . . . 108, 118, 120 cntlb . . . . . . . . . 61, 64, 105, 108, 112, 113, 114, 120, 121 register . . . . . . . . . . . . . . . . . . . . 108, 117 cold or warm start . . . . . . . . . . . . . . . . . . 45 comparator front end . . . . . . . . . . . . . . . . . 25 comparator inputs and outputs . . . . . . . . 25 comparator output . . . . . . . . . . . . 26, 39, 69 port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 40 comparator reference voltage . . . . . . . . . . 25 input . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 comparator1 . . . . . . . . . . . . . . . . . . . . . . . 37 comparator2 . . . . . . . . . . . . . . . . . . . . . . . 37 comparators, onboard . . . . . . . . . . . . . . . . 24 control register a . 25, 61, 63, 105, 111, 115 control register b . . . . . . . . 61, 64, 105, 108, 112, 113, 114, 120, 121 control registers . . . . . . . . . . . . . . . . . . . . 50 counter/timer 0 . . . . . . . . . . . . . . . . . . . . . 53 register . . . . . . . . . . . . . . . . . . . . . . . . 53 counter/timer 1 . . . . . . . . . . . . . . . . . . 24, 52 register . . . . . . . . . . . . . . . . . . . . . . . . 52 counter/timers . . . . . . . . . . . . . . . . . . . . . 34
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary i ndex 138 crystal . . . . . . . . . . . . . . . . . . . .43, 46, 71, 72 clock . . . . . . . . . . . . . . . . . . . . . . . .47, 49 operation . . . . . . . . . . . . . . . . . . . . . . . .41 oscillation . . . . . . . . . . . . . . . . . . . . . . .39 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 crystal 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .20 crystal 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .20 customer feedback form . . . . . . . . . . . .136 customer information . . . . . . . . . . . . . . . .136 d d0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 d1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 d2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 d3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 d4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 d5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 d6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 d7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41, 45 data memory . . . . . . . . .1, 20, 24, 30, 31, 34 select . . . . . . . . . . . . . . . . . . . . . . . . . .25 data strobe . . . . . . . . . . . . . . . . . . .12, 16, 20 dav1 . . . . . . . . . . . . . . . . . . . . . . . . . . .22, 55 dc electrical characteristics . . . . . . . . . . .76 decimal adjust flag . . . . . . . . . . . . . . . . . .59 divide ratio . . . . . . . . . . . . . . . .115, 121, 123 dm . . . . . . . . . . . . . . . . . . .25, 31, 55, 88, 90 dma applications . . . . . . . . . . . . . . . . .21, 22 document information . . . . . . . . . . . . . . . .135 document number description . . . . . . . . .135 ds . . . . . . . .12, 16, 20C22, 28, 41, 56, 87C90 e efr . . . . . . . . . . . . . . . . . . . . . . . . . . .63, 113 bit . . . . . . . . . . . . . . . .107C108, 118, 120 electrical characteristics . . . . . . . . . . . . . . .75 eprom protect . . . . . . . . . . . . . . . . .32, 102 erf . . . . . . . . . . . . . . . . . . . . . . . .1, 3, 32C33 error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 error flag reset . . . . . . . . . . . . .63, 112C113 expanded register file . . .1, 3, 32C33, 39, 60 bank fh . . . . . . . . . . . . . . . . . . . . . . . . .67 extended temperature range . . . . . . 81, 89 extension control register . . . . . . . . 65, 116 external clock divide-by-two . . . . . . . . . . 43 external clock generator . . . . . . . . . . 76, 81 external crystal oscillation . . . . . . . . . . . . . 39 external memory timing . . . . . . . . . . . . . . 55 external memory transfer . . . . . . . . . . . . . . 20 external program memory . . . . . . . 25, 31C32 external single-phase clock . . . . . . . . . . . . 20 external timing input . . . . . . . . . . . . . . . . . 52 f fe . . . . . . . . . . . . . . . . . . . . . . . . . . 113, 120 flag register . . . . . . . . . . . . . . . . . . . . . . . 59 floating node . . . . . . . . . . . . . . . . . . . . . . . 27 framing error . . . . . . . . . . . . . . 108, 117, 120 full-duplex uart . . . . . . . . . . . . . . . . . . . . 2 functional block diagram . . . . . . . . . . . . . . 4 g general-purpose registers . . . . . . . . . . . . 34 gnd . . . . . . . . 1, 5, 8, 12, 14, 16, 18, 20, 100 gpr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 h half carry flag . . . . . . . . . . . . . . . . . . . . . 59 halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 halt mode . . . . . . . . . . . . 39, 43, 47, 78, 83 handshake control . . . . . . . . . . . . . 20, 22, 23 lines . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 handshake mode . . . . . . . . . . . . . . . . . 23 handshake signal assignment . . . . . . . . . . 23 handshake signal direction . . . . . . . . . . . . 20 high-impedance state . . . . . . . . . . . . . 20C22 i icsp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 initialization routine . . . . . . . . . . . . . . . . . . 21 input buffers . . . . . . . . . . . . . . . . . . 20, 22C23
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary i ndex 139 input clock period . . . . . . . . . . . . . . . . .92, 95 input common mode . . . . . . . . . . . . . .79, 84 input high voltage . . . . . . . . . . . . . . . .76, 81 input leakage . . . . . . . . . . . . . . . . . . . .77, 82 input low voltage . . . . . . . . . . . . . . . . .76, 81 internal clock . . . . . . . . . . . . . . . . . .34, 39, 49 output . . . . . . . . . . . . . . . . . . . . . . . . . .51 interrupt edge . . . . . . . . . . . . . . . . . . . . . . .57 select . . . . . . . . . . . . . . . . . . . . . . . . . .37 interrupt group priority . . . . . . . . . . . . . . . .56 interrupt inputs . . . . . . . . . . . . . . . . . . . . . .37 falling-edge . . . . . . . . . . . . . . . . . . . . . .24 interrupt mask register . . . . . . . . . . . . . . . .58 interrupt priority register . . . . . . . . . . . . . .56 interrupt request . . . . . . . . . . . . . . . . .93, 96 register . . . . . . . . . . . . . . . . . . . . . . . . .57 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .36 asci . . . . . . . . . . . . . . . . . . . . . . . . . .109 edge-triggered . . . . . . . . . . . . . . . . . . . .24 external . . . . . . . . . . . . . . . . . . . . . . . . .39 receive shift register . . . . . . . . . . . .106 z8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 irq0 . . . . . . . . . . . . . . . . . .25, 36, 39, 57, 58 irq1 . . . . . . . . . . . . . . . . . .25, 36, 39, 57, 58 source . . . . . . . . . . . . . . . . . . . . . . . . . .25 irq2 . . . . . . . . . . . . . . . . . .25, 36, 39, 57, 58 irq3 . . . . . . . 25, 37, 39, 56, 58, 65, 67, 109, 117, . . . . . . . . . . . . . . . . . . . . . . . .119C121 irq4 . . . . . . . . . . . . . . . . . . . . . . . .34, 37, 57 irq5 . . . . . . . . . . . . . . . . . . . . .34, 37, 56C57 l lc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3, 38 network . . . . . . . . . . . . . . . . . . . . . . . . .20 oscillator . . . . . . . . . . . . . .39, 92, 95, 103 low-emi emission . . . . . . . . . . . . . . . . . . .41 low-emi mode . . . . . .22, 41, 76C77, 81C82 low-emi oscillator . . . . . . . . . . . . .39C41, 69 mode . . . . . . . . . . . . . . . . . . . . .41, 92, 95 low-emi output buffers . . . . . . . . . .20, 22C24 low-emi port 0 . . . . . . . . . . . . . . . . . . . . . .41 low-emi port 1 . . . . . . . . . . . . . . . . . . . . . .41 low-emi port 2 . . . . . . . . . . . . . . . . . . . . . .41 low-emi port 3 . . . . . . . . . . . . . . . . . . . . . 41 m memory address transfers . . . . . . . . . . . . . 20 mode select . . . . . . . . . . . . . . . . . . . . . . . . 63 mpbr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 mpe . . . . . . . . . . . . . . . . . . . . . . . . . . 63, 111 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 multiplexed address/data mode . . . . . . . . 22 multiplexed ports . . . . . . . . . . . . . . . . . . . . 22 multiprocessor bit receive (read only) . 113 multiprocessor bit received . . . . . . . 63, 112 multiprocessor bit transmit . . . . . . . . . . . 115 multiprocessor bit transmitter . . . . . . 64, 114 multiprocessor enable . . . . . . . . 63, 111, 112 multiprocessor mode . . . 105, 108, 112, 113, 115 n nibble-programmed input buffers . . . . . . . . 20 o offset voltage . . . . . . . . . . . . . . . . . . . 77, 82 onboard comparators . . . . . . . . . . . . . . . . 24 on-chip oscillator . . . . . . . . . . . . . . . 3, 20, 38 oscillator operational mode . . . . . . . . . . 103 oscillator startup time . . . . . . . . . . . . 93, 96 output high voltage . . . . . . . . . . . 76, 77, 81 output leakage . . . . . . . . . . . . . . . . . . 78, 82 output low voltage . . . . . . . . . . . . . . . 77, 82 overflow flag . . . . . . . . . . . . . . . . . . . . . . 59 overrun error . . . . . . . . . . 105, 106, 108, 120 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 p p3m . . . . . . . . . . . . . . . 24, 25, 28, 31, 46, 54 parallel-resonant crystal . . . . . . . . . . . . . . 20 parity error . . . . . . . . . . . . . . . . . . . 108, 120 parity even/odd . . . . . . . . . . . . . . . 113, 115
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary i ndex 140 part number description . . . . . . . . . . . . . .134 pcon . . . . . . . . . . . . . . . . . . . . . . .28, 33, 39 register . . . . . . . . . . . . . . . . . . .22, 39, 41 register bit . . . . . . . . . . . . . . . . . . . . . .25 pe . . . . . . . . . . . . . . . . . . . . . . . . . . .113, 120 peo . . . . . . . . . . . . . . . . . . . . .113, 115, 120 pin description . . . . . . . . . . . . . . . . . . . . . . .5 plastic standard flow . . . . . . . . . . . . . . . .134 por . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 por only . . . . . . . . . . . . . . . . .43, 45, 71, 72 port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mode register . . . . . . . . . . . . . . . . . . . .21 open-drain . . . . . . . . . . . . . . . . . . . . . .41 pull-ups . . . . . . . . . . . . . . . . . . . . . . .103 port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 open-drain . . . . . . . . . . . . . . . . . . . . . .40 pull-ups . . . . . . . . . . . . . . . . . . . . . . .103 port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 mode register . . . . . . . . . . . . . . . . . . . .54 pull-ups . . . . . . . . . . . . . . . . . . . . . . .103 port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 mode register . . . . . . . . . . .24, 31, 54, 55 mode register . . . . . . . . . . . . . . . . . . . .25 pin assignments . . . . . . . . . . . . . . . . . .25 port configuration register . . . . . . . . . .39, 69 power supply . . . . . .5, 6, 7, 9, 11, 13, 15, 17 power-on cycle . . . . . . . . . . . . . . . . . . . . . .42 power-on reset . .3, 27, 29, 38, 47, 120, 121 delay . . . . . . . . . . . . . . . . . . . . . . . .94, 96 precharacterization product . . . . . . . . . . .134 prescale bit . . . . . . . . . . . . . . . . . . . . . . . .115 prescale factor . . . . . . . . . . . . . . . . . . . . .115 prescaler . . . . . . . . . . . . . . . . . . . . . . .43, 123 prescaler 0 register . . . . . . . . . . . . . . . . . .53 prescaler 1 register . . . . . . . . . . . . . . . . . .52 prescaler modulo . . . . . . . . . . . . . . . . .52, 53 prescaler, 6-bit programmable . . . . . . . .3, 34 prescaler, t1 . . . . . . . . . . . . . . . . . . . . . . . .34 problem description or suggestion . . . . .136 product information . . . . . . . . . . . . . . . . . .136 program memory . . . . . . . . . . . . . . .1, 30, 102 vector location . . . . . . . . . . . . . . . . . . . .37 external . . . . . . . . . . . . . . . . . . . . . . . . .25 programmable watch-dog timers . . . . . . . .1 r ram protect . . . . . . . . . . . . . . . . 32, 58, 102 rc . . . . . . . . . . . . . . . . . . . . . . . 3, 47, 92, 95 circuit, external . . . . . . . . . . . . . . . . . 103 network . . . . . . . . . . . . . . . . . . . . . . . . 20 oscillator . . . . . . . . . . . . . . . . . 38C39, 46 rc oscillator enabled . . . . . . . . . 103 rc select for wdt . . . . . . . . . . . . . . . . . . 46 rdr . . . . . . . . . . . . . . . . . . . . . . . 61, 62, 111 rdrne . . . . . . . . . . . . . . . . . . 111, 119, 120 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 rdy1 . . . . . . . . . . . . . . . . . . . . . . . . . . 22, 55 re . . . . . . . . . . . . . . . . . . . . . . . . 25, 63, 105 read operation . . . . . . . . . . . . . . . . . . . . . 20 read/write signal . . . . . . . . . . . . . . . . . 20 receive data fifo . . . . . . . . . . . . . . . . . 106 receive data register . . . . . . . . . . . . 62, 111 receive data register not empty . . 111, 119 receive shift register . . . . . . . . . . . . . . . 105 receiver enable . . . . . . . . . . . . . . . . . . . 112 receiver interrupt enable . . . . . . . . . . . . 120 register file . . . . . . . . . . . . . . . . . . . . . 1, 32 register pointer register . . . . . . . . . . . . . 59 reset . . . . . . . . . . . . . . . . . . . . . . . . 27, 108 delay . . . . . . . . . . . . . . . . . 42, 45, 94, 96 reset input current . . . . . . . . . . . . . . . 78, 83 reset input high voltage . . . . . . . . . . . 77, 82 reset input low voltage . . . . . . . . . . . 77, 82 reset output low voltage . . . . . . . . . . 77, 82 reset pin . . . . . . . . . . . . . . . . . . . 27, 30, 75 return information . . . . . . . . . . . . . . . . . . 136 rie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 rom mode . . . . . . . . . . . . . . . 20C21, 30C31 rom pin . . . . . . . . . . . . . . . . . . . . . . . . . . 20 rom selectivity . . . . . . . . . . . . . . . . . . . . . . 1 romless mode . . . . . . . . . . . . . . . . . . 21, 34 romless pin . . . . . . . . . . . . . . . . . . . . . . . 20 romless selectivity . . . . . . . . . . . . . . . . . . . 1 rx interrupt on start . . . . . . . . . . . . . . . . 117 rx state . . . . . . . . . . . . . . . . . . . . . . . . . 117 s schmitt-triggered input buffers . . . . . . 20, 22
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary i ndex 141 sclk . . 41, 43, 46C47, 71, 73, 87, 89, 92, 95, 108, 116C117, 121, 123 sclk/tclk divide-by-16 select . . . . . . . .43 send break . . . . . . . . . . . . . . . . . . . . . . . .118 sign flag . . . . . . . . . . . . . . . . . . . . . . . . . . .59 smr . . . . . .28, 33, 37C38, 41, 46, 70, 92, 95 smr2 . . . . . . . . . . . . . . . . . . . .33, 37, 45, 72 speed select . . . . . . . . . . . . . . . . . . . . . . .116 stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 stack pointer . . . . . . . . . . . . . . . . . . . . .34, 60 high register . . . . . . . . . . . . . . . . . . . .60 low register . . . . . . . . . . . . . . . . . . . . .60 stack selection . . . . . . . . . . . . . . . . . . . . . .56 standard output . . . . . . . . . . . . . . . . . .40, 69 standard temperature range . . . . . . .76, 87 standard test conditions . . . . . . . . . . . . .100 standby current . . . . . . . . . . . .78, 79, 83, 84 stat . . . . . . . . . . . . . . . . . . . . . . .61, 67, 119 stat register . . . . . . .67, 111, 113, 119C121 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 stop delay . . . . . . . . . . . . . . . . . . . . . .46, 71 stop mode . . 28, 39, 45-47, 71, 79, 84, 103 delay . . . . . . . . . . . . . . . . . . . . . . . .92, 95 stop-mode recovery . 27, 34, 38C39, 42C43, 47, 50, 61, 68, 71 delay select . . . . . . . . . . . . . . . . . . . . .45 edge select . . . . . . . . . . . . . . . . . . . . . .45 register . . . . . . . . . . . . . . . . . . . . . .41, 70 register 1 . . . . . . . . . . . . . . . . . . . . . . .70 register 2 . . . . . . . . . . . . . . . . . . . .45, 72 source . . . . . . . . . . . . . .29, 37, 43, 45, 71 source 2 . . . . . . . . . . . . . . . . . . . . . . . .72 width spec . . . . . . . . . . . . . . . . . . .93, 96 storage temperature . . . . . . . . . . . . . . . . .75 supply current . . . . . . . . . . . . . . . . . . .78, 83 system clock . . . . . . . . . . . . . .41, 43, 47, 121 option, wdt driven by . . . . . . . . . .103 source option . . . . . . . . . . . . . . . . .103 system clocks, internal . . . . . . . . . . . . . . . .46 t t0 count . . . . . . . . . . . . . . . . . . . . . . . . . . .51 t0 output . . . . . . . . . . . . . . . . . . . . . . . . . .51 t0 output . . . . . . . . . . . . . . . . . . . . . . . . . . 34 t0 prescaler . . . . . . . . . . . . . . . . . . . . . . . . 34 t1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 count . . . . . . . . . . . . . . . . . . . . . . . . . . 51 prescaler . . . . . . . . . . . . . . . . . . . . . . . 34 tclk . . . . . . . . . . . 41, 43, 71, 87, 89, 92, 95 tdr . . . . . . . . . . . . . . . . . . . . . . . 61, 62, 110 tdre . . . . . . . . . . . . . . . . . . . . 113, 120, 121 te . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 63 tie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 time constant register high . . . . . . 66, 118 time constant register low . . . . . . . 66, 118 timer input . . . . . . . . . . . . . . . . . . . . . 92, 95 timer mode register . . . . . . . . . . . . . . . . . 51 t in . . . . . . . . . . . . . . . . . . . . . . 25, 36, 52, 54 mode . . . . . . . . . . . . . . . . . . . . . . . 34, 51 total power dissipation . . . . . . . . . . . . . . . 75 t out . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 54 mode . . . . . . . . . . . . . . . . . . . . . . . . . . 51 transmit data register . . . . . . . 62, 105, 110 empty . . . . . . . . . . . . . . . . . . . . . . . . 120 transmit interrupt enable . . . . . . . . . . . . 121 transmit shift register . . . . . . . . . . . . . . 105 transmitter enable . . . . . . . . . . . . . . 63, 112 trigger input . . . . . . . . . . . . . . . . . . . . . 34, 51 two-nop delay . . . . . . . . . . . . . . . . . . . . . 26 u uart . . . . . . . . . . . . . . . . . . . . . 2, 37, 39, 57 onboard asci . . . . . . . . . . . . . . . . . . . 25 user flags . . . . . . . . . . . . . . . . . . . . . . . . . 59 v vbo . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 104 v cc . . . . . . . 1, 5C7, 9, 11, 13, 15, 17, 20, 34, 47, 76C77, 87, 89, 98C99, 101, 104 low-voltage protection . . . . . . . . . . . . 48 low voltage protection voltage . . 80, 85 power-on reset . . . . . . . . . . . . . . . . . 38 verify register . . . . . . . . . . . . . . . . . . . 33, 70 vfy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 voltage comparator . . . . . . . . . . . . . . . . . 48
z86e12x/z86e13x/z86e14x the muze family of z8 microcontrollers ps004005-1100 preliminary i ndex 142 w wake-up circuitry . . . . . . . . . . . . . . . . . . . . . .1 watch-dog timer . . .1, 3, 29, 72, 93, 96, 103 mode register . . . . . . . . . . . . . . . . .46, 72 reset . . . . . . . . . . . . . . . . . . . . . . . . . . .27 wdt mode . . . . . . . . . . . . . . . . . . . . . . . .103 wdt time select . . . . . . . . . . . . . . . . . . . .47 wdt time-out . . . . . . . . . . . . . .38, 39, 46, 47 wdtmr . . . . . . . . . . . . . . . . . .28, 33, 46, 72 during halt . . . . . . . . . . . . . . . . . . . . .47 during stop . . . . . . . . . . . . . . . . . . . . .47 register accessibility . . . . . . . . . . . . . .47 working register pointer . . . . . . . . . . . . . .59 write operations . . . . . . . . . . . . . . . . . . . .20 x x in . . . . . . 5, 7, 12, 15, 20, 38, 72, 75C76, 81 x in pin . . . . . . . . . . . . . . . . . . . . . . . . 46, 103 x in , external pin . . . . . . . . . . . . . . . . . . . . . 47 x out . . . . . . . . . . 5, 7, 12, 15, 20, 38, 76, 81 x out pin . . . . . . . . . . . . . . . . . . . . . . . . . 103 z z8 mcu . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 zero flag . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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